Unit 1: Fundamentals of Electrical Laws, Semiconductor Devices and its Applications

1. Electrical Engineering Fundamentals and Network Variables

Modern electronic systems, from embedded microcontrollers to complex communication networks, rely upon foundational principles of electrical physics. Electrical circuit analysis evaluates how energy transforms, distributes, and dissipates across interconnected physical media.

1.1 Fundamental Charge, Current, Voltage, and Power

• Electric Charge ($Q$): The intrinsic physical property of atomic matter responsible for electromagnetic interactions. Quantized in units of elementary electron charge (e pprox 1.602 \times 10^{-19}\text{ C}), its SI unit is the Coulomb ($\text{C}$).
• Electric Current ($I$): The instantaneous time-rate of charge transfer passing through a defined cross-sectional plane:
  $I = \frac{dq}{dt} \quad [\text{Amperes, A}]$
  A steady direct current (DC) of one Ampere transfers one Coulomb of net charge per second ($1\text{ A} = 1\text{ C/s}$). By international convention, current direction corresponds to positive charge trajectory, counter to physical electron drift.
• Electric Potential and Voltage ($V$): The work required ($dW$) to displace an infinitesimal test charge ($dq$) through an electrostatic field between reference point $a$ and target node $b$:
  $V_{ab} = \frac{dW}{dq} \quad [\text{Volts, V}]$
  One Volt represents one Joule of electrostatic potential work executed per Coulomb of charge ($1\text{ V} = 1\text{ J/C}$).
• Electric Power ($P$) and Energy ($W$): The instantaneous rate of energy expenditure or conversion:
  $P(t) = V(t) \cdot I(t) = \frac{dW}{dt} \quad [\text{Watts, W}]$
  By the Passive Sign Convention (PSC), when conventional current enters the positive potential terminal of a two-terminal element, power $P > 0$ denotes absorbed power (dissipation in resistors or charging in storage elements). When current departs the positive terminal, $P < 0$ denotes supplied power (batteries, generating sources).
  Accumulated energy over duration $T$ equals:
  $W = \int_{0}^{T} P(t) \, dt \quad [\text{Joules, J}]$

1.2 Classification of Circuit Elements

CODECopy Code
                    Circuit Elements
                     /            \
              Active                Passive
            /        \            /    |    \
     Independent   Dependent  Resistor Inductor Capacitor
     (Ideal V & I) (Controlled) (Ohmic)  (L)       (C)

• Active Elements: Devices capable of introducing net average energy into a network indefinitely (e.g., chemical batteries, photovoltaic cells, operational amplifiers, transistors).
  • Independent Sources: Terminal parameters ($V_s$ or $I_s$) remain strictly independent of network variables.
  • Dependent (Controlled) Sources: Terminal output relies upon a governing voltage or current elsewhere in the circuit:
    1. Voltage-Controlled Voltage Source (VCVS): $v = \mu \cdot v_x$
    2. Voltage-Controlled Current Source (VCCS): $i = g_m \cdot v_x$
    3. Current-Controlled Voltage Source (CCVS): $v = r_m \cdot i_x$
    4. Current-Controlled Current Source (CCCS): $i = \beta \cdot i_x$
• Passive Elements: Components unable to generate net electrical power, functioning solely to absorb, dissipate, or store energy (resistors, inductors, capacitors).

1.3 Ohm's Law and Resistive Properties

At steady-state temperature, the electric current conducting through an ideal linear conductor is directly proportional to the applied potential difference across its terminals:
$V = I \cdot R \iff I = G \cdot V$
Where $R$ is electrical resistance measured in Ohms ($\Omega$), and $G = 1/R$ is electrical conductance measured in Siemens ($\text{S}$ or $\mho$).

For a uniform conductor of length $L$, cross-sectional area $A$, and material resistivity $\rho$ ($\Omega \cdot \text{m}$):
$R = \rho \frac{L}{A} = \frac{L}{\sigma A}$
Where $\sigma = 1/\rho$ represents material conductivity ($\text{S/m}$).

Limitations of Ohm's Law:

Ohm's Law is not a universal fundamental law of nature; rather, it is an empirical relation applicable strictly to linear, isotropic, bilateral conductors operating at constant thermodynamic temperature. It fails completely in:

1. Non-linear components: Semiconductor diodes, bipolar transistors, thyristors, and vacuum tubes where $V-I$ characteristics are exponential or threshold-governed.
2. Arc discharges and ionized gases: Where negative incremental resistance regimes occur.
3. Thermal drift regimes: Where self-heating alters carrier scattering rates, causing non-linear curvature in tungsten lamp filaments.

2. DC Network Theorems and Systematic Circuit Analysis

Complex networks comprising multiple branches, meshes, and energy sources require systematic reduction techniques based on fundamental conservation laws.

2.1 Kirchhoff's Fundamental Laws

• Kirchhoff's Current Law (KCL): Rooted in the conservation of electric charge. Charge cannot accumulate indefinitely at a dimensionless mathematical junction (node). The algebraic sum of all currents entering and leaving any circuit node is identically zero:
  $\sum_{k=1}^{n} I_k = 0 \iff \sum I_{\text{entering}} = \sum I_{\text{leaving}}$
• Kirchhoff's Voltage Law (KVL): Rooted in the conservation of electrostatic energy. The electrostatic field is conservative; moving a unit charge along any continuous closed trajectory returns the test charge to its initial potential. Hence, the algebraic sum of directed potential drops and electromotive forces (EMFs) around any closed loop is zero:
  $\sum_{k=1}^{m} V_k = 0 \iff \sum V_{\text{rises}} = \sum V_{\text{drops}}$

2.2 Voltage and Current Division Principles

2.3 Comprehensive Network Theorems

1. Thevenin's Theorem

Any linear, bilateral, two-terminal resistive network containing independent and dependent sources can be replaced at terminals $A-B$ by an equivalent circuit consisting of a single open-circuit voltage source $V_{th}$ in series with an equivalent resistance $R_{th}$.

• Open-Circuit Voltage ($V_{th}$): The potential measured between load terminals when the external load resistance $R_L$ is detached ($R_L \to \infty$).
• Thevenin Resistance ($R_{th}$): The equivalent input resistance observed across disconnected terminals $A-B$ with all independent voltage sources replaced by short circuits ($0\text{ V}$) and independent current sources replaced by open circuits ($0\text{ A}$). If dependent sources exist, inject a test source ($V_{test}$ or $I_{test}$) and calculate $R_{th} = V_{test} / I_{test}$.
• Load Current Formulation:
  $I_L = \frac{V_{th}}{R_{th} + R_L}, \quad V_L = I_L \cdot R_L = V_{th} \left( \frac{R_L}{R_{th} + R_L} \right)$

CODECopy Code
        Thevenin Equivalent                      Norton Equivalent
           R_th           A                             A
       ---[====]---o-----o                        o-----o
      |                  |                        |     |
     (~) V_th           [ ] R_L              (^) [ ]   [ ] R_L
      |                  |                   I_N [ ]   |
      -------------------o                        o-----o
                          B                             B

2. Norton's Theorem

Any linear two-terminal network can be modeled as an equivalent ideal current source $I_N$ connected in parallel with an equivalent Norton resistance $R_N$.

• Short-Circuit Current ($I_N$): Current flowing through a zero-resistance short placed across terminals $A-B$.
• Source Transformation Relation:
  $R_N = R_{th}, \quad I_N = \frac{V_{th}}{R_{th}} \iff V_{th} = I_N \cdot R_N$

3. Maximum Power Transfer Theorem (MPTT)

In a linear DC circuit delivering power to a variable resistive load $R_L$, maximum power absorption occurs when load resistance equals the internal Thevenin source resistance:
$R_L = R_{th}$
Under matched conditions ($R_L = R_{th}$), the peak power transferred evaluates to:
$P_{L(\max)} = I_L^2 R_L = \left(\frac{V_{th}}{2 R_{th}}\right)^2 R_{th} = \frac{V_{th}^2}{4 R_{th}}$
Crucial Engineering Insight: Under maximum power transfer conditions, circuit transmission efficiency is precisely $50\%$ because identical power dissipates internally across $R_{th}$. In electrical power grid transmission, impedance matching is intentionally avoided to preserve high transmission efficiency ($> 90\%$), whereas in RF, telecom, and sensor instrumentation, matching is mandatory to avoid reflected wave distortion.

4. Superposition Theorem

In any linear, bilateral network containing multiple independent energy sources, the net electrical response (voltage or current) across any branch equals the algebraic summation of responses elicited by each independent source acting individually, while all remaining independent sources are deactivated (voltage sources shorted, current sources opened). Note: Superposition applies strictly to linear variables ($V$ and $I$), not non-linear quantities like electric power ($P \propto I^2$).

3. Semiconductor Physics and Charge Transport Dynamics

Electronic solid-state devices control the flow of electric charge using crystalline semiconductors whose conductivity spans the gap between metals and dielectric insulators.

3.1 Energy Band Theory of Solids

Quantum mechanical interactions split discrete atomic electron energy levels into continuous permitted bands separated by forbidden energy gaps ($E_g$):

• Conduction Band: High-energy permitted state where electrons move freely under electric fields.
• Valence Band: Lower-energy band occupied by covalent bonding electrons.
• Forbidden Bandgap ($E_g$): Energy differential between valence band ceiling ($E_v$) and conduction band floor ($E_c$).

CODECopy Code
      Conductors               Semiconductors             Insulators
  ===================        ===================      ===================
  | Conduction Band |        | Conduction Band |      | Conduction Band |
  |=== Overlapping ==        ===================      ===================
  |  Valence Band   |                 |                        |
  ===================                 | Eg ~ 1.1 eV            | Eg > 5 eV
                             ===================               |
                             |  Valence Band   |      ===================
                             ===================      |  Valence Band   |
                                                      ===================

• Metals (Conductors): Conduction and valence bands overlap ($E_g = 0\text{ eV}$). Vast density of conduction electrons at all temperatures. Resistivity displays a positive temperature coefficient (PTC).
• Semiconductors: Narrow bandgap ($E_g \approx 1.12\text{ eV}$ for Silicon, $0.66\text{ eV}$ for Germanium, $1.42\text{ eV}$ for Gallium Arsenide at $300\text{ K}$). Insulators at $0\text{ K}$, displaying negative temperature coefficient (NTC) as thermal excitation liberates electron-hole pairs.
• Insulators: Very wide bandgap ($E_g > 5\text{ eV}$ for Diamond and $\text{SiO}_2$). Valence electrons remain locked in covalent lattices under normal fields.

3.2 Intrinsic and Extrinsic Semiconductors

Intrinsic (Pure) Semiconductors

Pure, defect-free crystalline Silicon where electrical conduction originates solely from thermal generation of electron-hole pairs:
$n = p = n_i$
Where $n$ is free electron concentration ($\text{cm}^{-3}$), $p$ is hole concentration ($\text{cm}^{-3}$), and $n_i$ represents intrinsic carrier density ($n_i \approx 1.5 \times 10^{10}\text{ cm}^{-3}$ for Silicon at room temperature).

Extrinsic (Doped) Semiconductors

Intentional introduction of selected foreign impurity atoms into the crystalline matrix (doping ratio $\sim 1:10^6$) dramatically augments majority carrier concentration:

1. N-Type Semiconductor:
   • Doped with pentavalent donor atoms (Phosphorus, Arsenic, Antimony) possessing 5 valence electrons.
   • Four electrons form covalent bonds; fifth electron easily ionizes into the conduction band at room temperature ($E_d \approx 0.05\text{ eV}$ below $E_c$).
   • Creates fixed positive donor ions ($N_D^+$) and mobile conduction electrons.
   • Majority carriers: Electrons ($n \approx N_D$); Minority carriers: Holes ($p \approx n_i^2 / N_D$).
2. P-Type Semiconductor:
   • Doped with trivalent acceptor atoms (Boron, Gallium, Indium) possessing 3 valence electrons.
   • Captures valence electrons to complete tetrahedral bonds, generating positive holes.
   • Creates fixed negative acceptor ions ($N_A^-$) and mobile holes.
   • Majority carriers: Holes ($p \approx N_A$); Minority carriers: Electrons ($n \approx n_i^2 / N_A$).

Mass Action Law:

Under thermodynamic equilibrium, the product of equilibrium electron and hole densities is invariant at a fixed temperature, regardless of dopant concentration:
$n \cdot p = n_i^2(T)$

4. The PN Junction Diode and Non-Linear V-I Characteristics

When a P-type semiconductor and an N-type semiconductor are united in a single monocrystalline lattice, a metallurgical PN junction forms.

4.1 Formation of the Depletion Region and Built-in Potential

CODECopy Code
          P-Region                  Depletion Layer                 N-Region
    +-------------------+-------------------------------------+-------------------+
    |    -      -       |      -      -   |   +      +        |    +      +       |
    |  ( - )  ( - )     |    ( - )  ( - ) | ( + )  ( + )      |  ( + )  ( + )     |
    |    o      o       |      o      o   |   .      .        |    .      .       |
    |  Holes (Major)    |  Fixed Acceptor | Fixed Donor Ions  | Electrons (Major) |
    +-------------------+-------------------------------------+-------------------+
                                  <-------- Built-in E-field
                                  <-- V_bi Barrier Potential

1. Diffusion Current: Huge carrier gradient causes mobile holes in P-region to diffuse across the junction into N-region, while electrons in N-region diffuse into P-region.
2. Recombination and Space Charge Formation: Diffusing carriers recombine near the interface, unmasking motionless ionized impurity cores: negative acceptor ions ($N_A^-$) on the P-side and positive donor ions ($N_D^+$) on the N-side.
3. Depletion Layer (Space Charge Region): A region void of free mobile charge carriers, occupied solely by fixed ionic charges.
4. Built-in Electric Field and Drift: The ionic space charge induces an electric field pointing from N to P. This field exerts electrostatic force driving opposing drift currents.
5. Dynamic Equilibrium: Diffusion balances drift; net current is zero. The resulting contact barrier potential ($V_{bi}$) is:
   $V_{bi} = V_T \ln \left( \frac{N_A N_D}{n_i^2} \right)$
   Nominally, $V_{bi} \approx 0.7\text{ V}$ for Silicon and $0.3\text{ V}$ for Germanium at $300\text{ K}$.

4.2 Biasing Regimes and Shockley Equation

• Zero Bias ($V = 0\text{ V}$): Barrier potential blocks diffusion; drift equals diffusion; $I_{net} = 0$.
• Forward Bias ($V_D > 0\text{ V}$): Positive potential applied to P-anode, negative to N-cathode. External field opposes built-in field; depletion width shrinks; barrier height drops to $(V_{bi} - V_D)$. Exponential forward diffusion current surges once $V_D$ exceeds the "knee" or cut-in voltage ($V_\gamma \approx 0.7\text{ V}$ for Si).
• Reverse Bias ($V_D < 0\text{ V}$): Positive potential to N-cathode, negative to P-anode. External field reinforces built-in field; depletion layer broadens; barrier height rises to $(V_{bi} + |V_D|)$. Diffusion ceases; tiny reverse saturation current ($I_0$) flows, generated solely by thermal minority carrier drift ($I_0 \sim \text{nA}$ for Si, $\mu\text{A}$ for Ge).

Shockley Ideal Diode Equation:

$I_D = I_0 \left( e^{\frac{V_D}{\eta V_T}} - 1 \right)$
Where:

• $I_0$ = Reverse saturation leakage current.
• $\eta$ = Ideality factor ($1$ for Ge; $\approx 1$ to $2$ for Si depending on current level).
• $V_T$ = Thermal voltage:
  $V_T = \frac{k T}{q} \approx 25.86\text{ mV} \approx 26\text{ mV at } 300\text{ K}$
• Incremental / Dynamic AC Resistance:
  $r_d = \frac{d V_D}{d I_D} = \frac{\eta V_T}{I_D + I_0} \approx \frac{\eta V_T}{I_D}$

4.3 Reverse Breakdown Mechanisms: Zener vs Avalanche

When reverse voltage exceeds a critical threshold ($V_{BR}$), current multiplies abruptly without substantial voltage increment:

5. Diode Circuit Applications: Rectifiers, Filters, and Regulators

5.1 Rectifier Topologies Comparison

Rectifiers convert bidirectional alternating current (AC) into unidirectional pulsating direct current (DC).

CODECopy Code
  Half-Wave Rectifier         Center-Tapped Full-Wave          Bridge Full-Wave
      D1                                D1                           D1     D2
  ---|>|----.---             ---.---|>|---.---            .-----.---|>|--.--|>|---.
            |                   |         |               |     |        |        |
    (AC)   [ ] R_L        (AC) ( )       [ ] R_L    (AC) ( )    |       [ ] R_L   |
            |                   |         |               |     |        |        |
  ----------'---             ---o---.-----'---            '-----o---|<|--'--|<|---'
                              Center-Tap (GND)                      D4      D3

5.2 Smoothing Filter Circuits

Pulsating DC contains significant AC harmonics described by Fourier series. Shunt capacitor filters connect a large electrolytic capacitor in parallel with $R_L$:

• During the positive voltage crest, the diode conducts, charging capacitor $C$ to peak voltage $V_m$.
• As input falls below $V_m$, the diode reverse-biases; the capacitor discharges slowly into load $R_L$ with time constant $\tau = R_L C$.
• Ripple factor for full-wave bridge rectifier with shunt $C$ filter:
  $\gamma \approx \frac{1}{4 \sqrt{3} f C R_L}$
  To minimize ripple, engineer large capacitance $C$ and heavy load resistance $R_L$.

5.3 Zener Diode as a Shunt Voltage Regulator

A Zener diode biased in its reverse breakdown region maintains a virtually invariant terminal voltage $V_Z$ despite variations in unregulated input voltage $V_{in}$ or load current $I_L$.

• Circuit configuration: Series ballast resistor $R_s$ limits current into parallel zener and load:
  $I_s = I_Z + I_L$
  $R_s = \frac{V_{in} - V_Z}{I_s} = \frac{V_{in} - V_Z}{I_Z + I_L}$
• Design Bounds:
  • $R_{s(\max)} = \frac{V_{in(\min)} - V_Z}{I_{Z(\min)} + I_{L(\max)}}$ (guarantees zener remains in breakdown at minimum input and maximum load).
  • $R_{s(\min)} = \frac{V_{in(\max)} - V_Z}{I_{Z(\max)} + I_{L(\min)}}$ (prevents thermal destruction of zener when $I_L = 0$).
    $P_{Z(\max)} = V_Z \cdot I_{Z(\max)}$

6. Bipolar Junction Transistors (BJT) Architecture and Configurations

The Bipolar Junction Transistor is a three-terminal, current-controlled active device consisting of two back-to-back PN junctions sharing a microscopic central layer.

6.1 Physical Construction and Doping Asymmetry

CODECopy Code
               Emitter (E)             Base (B)             Collector (C)
            +----------------+-----------------------+------------------------+
   NPN:     |     N-type     |        P-type         |         N-type         |
            | Heavily Doped  | Lightly Doped, Narrow | Moderately Doped, Wide |
            +----------------+-----------------------+------------------------+
                   |                     |                        |
                   E                     B                        C

1. Emitter (E): Heavily doped ($N^{++}$) to inject a copious density of majority carriers into the base. Moderate physical geometry.
2. Base (B): Lightly doped ($P^-$) and physically microscopic (fractions of a micrometer). Designed to ensure $> 95-99\%$ of injected carriers traverse through to the collector without recombining.
3. Collector (C): Moderately doped to collect minority carriers swept across the base-collector junction. Fabricated with the largest physical surface area to dissipate thermal power ($P_D = V_{CE} \cdot I_C$).

6.2 BJT Operating Modes

6.3 Operating Configurations and Current Gain Relationships

CODECopy Code
      Common Base (CB)          Common Emitter (CE)         Common Collector (CC)
           C                         C                           E
           |                         |                           |
         --|\                     --|\                        /|--
       B   |  \                 B   |  \                    B  / |
     --o---|   > E             --o---|   > E              --o---|   > C
           |                         |                           |

1. Common Base (CB):
   • Base common to input and output.
   • Input current: $I_E$; Output current: $I_C$.
   • Current gain (Alpha, $\alpha$):
     $\alpha = \left. \frac{\Delta I_C}{\Delta I_E} \right|_{V_{CB} = \text{const}} \approx \frac{I_C}{I_E}$
     Since $I_E = I_B + I_C$ and $I_B > 0$, $\alpha$ is always slightly less than unity ($0.95 \le \alpha \le 0.998$).
   • Characteristics: Low input impedance ($10 - 50\,\Omega$), very high output impedance ($1\text{ M}\Omega$), non-inverting voltage gain, unity current gain.
2. Common Emitter (CE):
   • Emitter common to input and output.
   • Input current: $I_B$; Output current: $I_C$.
   • Current gain (Beta, $\beta$ or $h_{fe}$):
     $\beta = \left. \frac{\Delta I_C}{\Delta I_B} \right|_{V_{CE} = \text{const}} \approx \frac{I_C}{I_B}$
     Typically ranges from $20$ to $500$.
   • Mathematical interrelation:
     $I_C = \alpha I_E = \alpha (I_B + I_C) \implies I_C(1 - \alpha) = \alpha I_B$
     $\beta = \frac{\alpha}{1 - \alpha} \iff \alpha = \frac{\beta}{\beta + 1}$
   • Total collector current with leakage:
     $I_C = \beta I_B + I_{CEO} = \beta I_B + (1 + \beta)I_{CBO}$
   • Characteristics: Moderate input impedance ($1 - 2\text{ k}\Omega$), moderate output impedance ($50\text{ k}\Omega$), maximum power gain, $180^\circ$ phase inversion between input and output.
3. Common Collector (CC / Emitter Follower):
   • Collector common to AC input and output.
   • Input current: $I_B$; Output current: $I_E$.
   • Current gain (Gamma, $\gamma$):
     $\gamma = \frac{I_E}{I_B} = 1 + \beta = \frac{1}{1 - \alpha}$
   • Characteristics: Very high input impedance ($100 - 500\text{ k}\Omega$), very low output impedance ($10 - 100\,\Omega$), non-inverting unity voltage gain ($A_v \approx 1$). Used extensively as an impedance matching buffer between high-impedance sensors and low-impedance loads.

7. Common Pitfalls and Exam Traps

1. Confusion in Kirchhoff's Law Conservation Principles:
   • KCL represents conservation of charge (not energy).
   • KVL represents conservation of energy (not charge).
2. Superposition and Power:
   • Superposition cannot calculate power directly: $P_{total} \neq P_1 + P_2$. You must find total voltage or total current via superposition first, then compute $P = I_{total}^2 R$.
3. Maximum Power Transfer Fallacy:
   • Maximum power transfer does not imply maximum efficiency. Matched efficiency is strictly $50\%$. Maximum efficiency ($100\%$) occurs when internal source resistance $R_{th} \to 0$.
4. Zener Voltage Regulation Condition:
   • A Zener diode cannot regulate if load resistance is too small; if $R_L$ pulls excessive current such that $I_Z < I_{Z(\min)}$, the diode drops out of breakdown into the reverse leakage regime.
5. BJT Region Identification:
   • If calculated collector current $I_C = \beta I_B$ produces a collector voltage lower than emitter voltage ($V_C < V_E$), the transistor is in saturation, not active mode! In saturation, $V_{CE}$ fixes at $0.2\text{ V}$, and $I_{C(sat)} < \beta I_B$.

8. Quick Reference Formula Cheat-Sheet