ECE213Semester 2 • 4 CreditsSpecialization Subjects

Digital Electronics

Comprehensive foundation in digital systems design, covering binary number systems, arithmetic codes, Boolean algebra, logic minimization (K-maps, Quine-McCluskey), combinational circuit design (adders, decoders, multiplexers), sequential logic circuits (latches, flip-flops, state machines), counters and registers, semiconductor memories (RAM, ROM), and programmable logic devices (PLAs, PALs, FPGAs).

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Unit 1:Unit 1: Number Systems
7 min read•High-Yield Unit Guide

Unit 1: Number Systems

Unit 1 Exam Focus & Core Takeaways

Review the core definitions, standard architectures, and syntax patterns below. Pay special attention to sections highlighted with bullet points for your mid-term and end-term subjective questions.

Unit 1: Number Systems, Signed Arithmetic, and Binary Codes


1. Introduction: Digital Systems and Information Representation

In modern electronics and computer architecture, information processing relies on digital systems—circuits and architectures that operate on discrete, quantized physical variables rather than continuously varying analog signals.

CODE
       Analog Continuous Waveform                     Digital Quantized Waveform
             +V |     _.-'''-._                           +V |    +------+      +------+
                |   .'         '.                            |    |      |      |      |
             0V +--'-------------'-.----------> t         0V +----+      +------+      +----> t
                |                   '.   .'                  |
             -V |                     '-'                 -V |
           (Infinite continuum of values)             (Discrete binary logic states: 0 & 1)

1.1 Advantages of Digital Over Analog Systems

  1. High Noise Immunity: Digital signals map voltages to wide discrete noise margins (e.g., in standard 5V TTL, any voltage between 2.0 V2.0\text{ V} and 5.0 V5.0\text{ V} is interpreted unambiguously as logic 1, while 0.0 V0.0\text{ V} to 0.8 V0.8\text{ V} is logic 0). Minor electrical fluctuations, crosstalk, and thermal noise do not alter the interpreted logic value.
  2. Deterministic Programmability and Automation: Digital processors execute software-defined algorithmic sequences with bit-exact reproducibility.
  3. High Integration Density and Scaling: Billions of complementary MOS (CMOS) transistors can be integrated onto a single silicon die without cascading drift or cumulative distortion.
  4. Error Detection and Correction: Digital information can be augmented with parity bits, checksums, and Hamming codes to detect and correct transmission or storage errors dynamically.

2. Positional Number Systems and Radix Representation

A positional number system represents a numerical magnitude as a weighted linear combination of digits, where the position of each digit determines its weight as a power of the radix (or base) rr.

2.1 Generalized Radix-r Polynomial Form

Any real number NN represented with base rr can be expressed in generalized polynomial notation:

Nr=(dn−1dn−2…d1d0.d−1d−2…d−m)rN_r = (d_{n-1} d_{n-2} \dots d_1 d_0 . d_{-1} d_{-2} \dots d_{-m})_r

where:

  • r≥2r \ge 2 is an integer representing the radix/base.
  • did_i are allowed digits in the set {0,1,2,…,r−1}\{0, 1, 2, \dots, r-1\}.
  • The radix point separates the integer part from the fractional part.
  • nn is the number of integer digits, and mm is the number of fractional digits.

The equivalent decimal quantitative value is obtained by expanding the sum:

V(N)=∑i=−mn−1di⋅ri=dn−1rn−1+⋯+d1r1+d0r0+d−1r−1+⋯+d−mr−mV(N) = \sum_{i=-m}^{n-1} d_i \cdot r^i = d_{n-1} r^{n-1} + \dots + d_1 r^1 + d_0 r^0 + d_{-1} r^{-1} + \dots + d_{-m} r^{-m}

CODE
+-------------------------------------------------------------------------------------------------+
|                                Standard Positional Number Systems                               |
+-------------+-------+-----------------------------+---------------------------------------------+
| System Name | Base  | Permitted Digit Set         | Primary Engineering Domain                  |
+-------------+-------+-----------------------------+---------------------------------------------+
| Binary      | r = 2 | {0, 1}                      | Fundamental semiconductor logic, ALUs, RAM  |
| Octal       | r = 8 | {0, 1, 2, 3, 4, 5, 6, 7}    | Compact binary shorthand (Unix permissions) |
| Decimal     | r = 10| {0, 1, 2, 3, 4, 5, 6, 7, 8, 9} Human arithmetic, user-facing displays     |
| Hexadecimal | r = 16| {0-9, A, B, C, D, E, F}     | Byte-aligned machine code, memory addresses |
+-------------+-------+-----------------------------+---------------------------------------------+

In hexadecimal notation, decimal values from 10 to 15 are denoted by letters:
A16=1010,B16=1110,C16=1210,D16=1310,E16=1410,F16=1510\text{A}_{16} = 10_{10}, \quad \text{B}_{16} = 11_{10}, \quad \text{C}_{16} = 12_{10}, \quad \text{D}_{16} = 13_{10}, \quad \text{E}_{16} = 14_{10}, \quad \text{F}_{16} = 15_{10}


3. Systematic Base Conversion Algorithms

Conversion between arbitrary number systems is a fundamental operation in digital computer interfaces and memory decoders.

CODE
                  +----------------------------------------------+
                  |               Decimal System                 |
                  +----------------------------------------------+
                        ^   |                      |    ^
        Polynomial      |   | Successive           |    | Polynomial
        Evaluation      |   | Division/Mult        |    | Evaluation
                        |   v                      v    |
                  +---------------+          +-------------------+
                  | Binary (r=2)  |<-------->| Hexadecimal (r=16)|
                  +---------------+  4-bit   +-------------------+
                          ^         Grouping
                          | 3-bit
                          v Grouping
                  +---------------+
                  |  Octal (r=8)  |
                  +---------------+

3.1 Decimal to Base-r Conversion

A decimal number with both integer and fractional components must be converted in two separate algorithmic steps:

  1. Integer Part (Successive Division Algorithm):

    • Divide the integer decimal value repeatedly by the target radix rr.
    • Record the integer quotient and the remainder RiR_i.
    • Terminate when the quotient reaches zero.
    • The remainders read from bottom to top (most recent remainder is the Most Significant Digit (MSD); first remainder is the Least Significant Digit (LSD)).
  2. Fractional Part (Successive Multiplication Algorithm):

    • Multiply the fractional part repeatedly by the target radix rr.
    • Extract the resulting integer part as the next fractional digit d−kd_{-k}.
    • Continue multiplying the remaining fractional component by rr until the fraction becomes zero or the desired bit precision is reached.
    • The digits are read in sequential order from top to bottom (first extracted integer is d−1d_{-1}, highest-weight fractional position).

Concrete Example: Convert (173.625)10(173.625)_{10} to Binary

  • Integer Conversion (17310173_{10}):

    • 173÷2=86173 \div 2 = 86 remainder 11 (LSD)
    • 86÷2=4386 \div 2 = 43 remainder 00
    • 43÷2=2143 \div 2 = 21 remainder 11
    • 21÷2=1021 \div 2 = 10 remainder 11
    • 10÷2=510 \div 2 = 5 remainder 00
    • 5÷2=25 \div 2 = 2 remainder 11
    • 2÷2=12 \div 2 = 1 remainder 00
    • 1÷2=01 \div 2 = 0 remainder 11 (MSD)
    • Result: (173)10=(10101101)2(173)_{10} = (10101101)_2
  • Fractional Conversion (0.625100.625_{10}):

    • 0.625×2=1.250  ⟹  digit 10.625 \times 2 = 1.250 \implies \text{digit } 1, fraction remains 0.2500.250
    • 0.250×2=0.500  ⟹  digit 00.250 \times 2 = 0.500 \implies \text{digit } 0, fraction remains 0.5000.500
    • 0.500×2=1.000  ⟹  digit 10.500 \times 2 = 1.000 \implies \text{digit } 1, fraction remains 0.0000.000 (Terminates)
    • Result: (0.625)10=(0.101)2(0.625)_{10} = (0.101)_2
  • Combined Result: (173.625)10=(10101101.101)2(173.625)_{10} = (10101101.101)_2

3.2 Power-of-Two Conversions (Binary, Octal, Hexadecimal)

Because 8=238 = 2^3 and 16=2416 = 2^4, conversions between Binary, Octal, and Hexadecimal do not require base-10 arithmetic; they are performed by direct bit grouping:

CODE
+-------------------------------------------------------------------------------------------------+
|                                 Direct Bit Grouping Equivalence                                 |
+---------+--------------------+---------+--------------------+---------+-------------------------+
| Octal   | Binary (3 bits)    | Hex     | Binary (4 bits)    | Hex     | Binary (4 bits)         |
+---------+--------------------+---------+--------------------+---------+-------------------------+
| 0       | 000                | 0       | 0000               | 8       | 1000                    |
| 1       | 001                | 1       | 0001               | 9       | 1001                    |
| 2       | 010                | 2       | 0010               | A (10)  | 1010                    |
| 3       | 011                | 3       | 0011               | B (11)  | 1011                    |
| 4       | 100                | 4       | 0100               | C (12)  | 1100                    |
| 5       | 101                | 5       | 0101               | D (13)  | 1101                    |
| 6       | 110                | 6       | 0110               | E (14)  | 1110                    |
| 7       | 111                | 7       | 0111               | F (15)  | 1111                    |
+---------+--------------------+---------+--------------------+---------+-------------------------+
  • Binary to Hexadecimal: Group bits into sets of 4, radiating outward from the binary point (leftward for integer, rightward for fraction), appending leading or trailing zeros as necessary. Replace each 4-bit nibble with its hexadecimal character.
    • Example: (1101101110.01011)2  ⟹  (0011 0110 1110 . 0101 1000)2=(36E.58)16(1101101110.01011)_2 \implies (0011\ 0110\ 1110\ .\ 0101\ 1000)_2 = (36\text{E}.58)_{16}.

4. Binary Arithmetic Operations

Binary arithmetic forms the operational core of the Arithmetic Logic Unit (ALU).

CODE
   Binary Addition Rules        Binary Subtraction Rules        Binary Multiplication Rules
      0 + 0 = 0 (Carry 0)          0 - 0 = 0 (Borrow 0)             0 x 0 = 0
      0 + 1 = 1 (Carry 0)          1 - 0 = 1 (Borrow 0)             0 x 1 = 0
      1 + 0 = 1 (Carry 0)          1 - 1 = 0 (Borrow 0)             1 x 0 = 0
      1 + 1 = 0 (Carry 1)          0 - 1 = 1 (Borrow 1)             1 x 1 = 1
      1 + 1 + 1 = 1 (Carry 1)

In binary multiplication, the product of two nn-bit integers produces a result of at most 2n2n bits, implemented via successive shift-and-add hardware registers.


5. Complements and Signed Number Systems

Digital circuits process both positive and negative integers. Rather than engineering separate hardware subtraction circuits, modern computers use complements to transform subtraction into addition:

A−B=A+(−B)A - B = A + (-B)

5.1 The Two Fundamental Complement Definitions

For any base-rr system with nn integer digits:

  1. Radix Complement (rr's Complement):
    [N]r=rn−N(for N≠0),[0]r=0[N]_r = r^n - N \quad (\text{for } N \ne 0), \quad [0]_r = 0

    • In base 10: 10's complement =10n−N= 10^n - N.
    • In base 2: 2's complement =2n−N= 2^n - N.
  2. Diminished Radix Complement ((r−1)(r-1)'s Complement):
    [N]r−1=(rn−1)−N[N]_{r-1} = (r^n - 1) - N

    • In base 10: 9's complement =(10n−1)−N= (10^n - 1) - N (subtract each digit from 9).
    • In base 2: 1's complement =(2n−1)−N= (2^n - 1) - N (invert all bits: 0→1,1→00 \to 1, 1 \to 0).

Crucial Relationship:
[N]r=[N]r−1+1  ⟹  2’s Complement=1’s Complement+1[N]_r = [N]_{r-1} + 1 \implies \text{2's Complement} = \text{1's Complement} + 1

5.2 Signed Binary Formats in Hardware

When representing signed integers in nn-bit words, the most significant bit (MSB) serves as the sign bit:

  • MSB=0  ⟹  Positive Number\text{MSB} = 0 \implies \text{Positive Number}
  • MSB=1  ⟹  Negative Number\text{MSB} = 1 \implies \text{Negative Number}
CODE
+-------------------------------------------------------------------------------------------------+
|                                 Comparison of n-bit Signed Formats                              |
+----------------------+--------------------+--------------------+--------------------------------+
| Representation       | Dynamic Range      | Zero Representation| Arithmetic Hardware Complexity |
+----------------------+--------------------+--------------------+--------------------------------+
| Signed Magnitude     | [ -(2^(n-1) - 1),  | Two zeros: +0 (000)| Separate adder & subtractor;   |
|                      |   +(2^(n-1) - 1) ] |            -0 (100)| complex sign comparison logic  |
+----------------------+--------------------+--------------------+--------------------------------+
| Signed 1's Complement| [ -(2^(n-1) - 1),  | Two zeros: +0 (000)| End-around carry addition;     |
|                      |   +(2^(n-1) - 1) ] |            -0 (111)| dual zero complicates logic    |
+----------------------+--------------------+--------------------+--------------------------------+
| Signed 2's Complement| [ -2^(n-1),        | Unique zero:       | Single standard binary adder;  |
|                      |   +(2^(n-1) - 1) ] |        0 (000...0) | subtraction is simple A + (~B+1)|
+----------------------+--------------------+--------------------+--------------------------------+
CODE
               Signed 2's Complement 4-bit Number Wheel
                                  0000 (0)
                           1111 (-1)   0001 (+1)
                      1110 (-2)             0010 (+2)
                  1101 (-3)                     0011 (+3)
                 1100 (-4)                       0100 (+4)
                  1011 (-5)                     0101 (+5)
                      1010 (-6)             0110 (+6)
                           1001 (-7)   0111 (+7)
                                 1000 (-8)
                 (Notice seamless wrap-around and unique zero)

5.3 2's Complement Subtraction and Overflow Conditions

To compute A−BA - B using nn-bit 2's complement:

  1. Form the 2's complement of BB, denoted B∗=B‾+1B^* = \overline{B} + 1.
  2. Compute S=A+B∗S = A + B^*.
  3. If an end-carry CoutC_{out} occurs past the nn-th bit, discard it. The result SS is mathematically correct.

Arithmetic Overflow Detection

Overflow occurs when an arithmetic operation produces a result that exceeds the representable range [−2n−1,+2n−1−1][-2^{n-1}, +2^{n-1}-1] of the nn-bit register.

  • Rule 1 (Sign Rule): Overflow can occur only when adding two operands of the same sign:
    • Positive ++ Positive yielding Negative   ⟹  \implies Overflow
    • Negative ++ Negative yielding Positive   ⟹  \implies Overflow
    • Adding operands of opposite signs can never overflow.
  • Rule 2 (Carry Rule for ALUs):
    Overflow Flag V=Cn⊕Cn−1\text{Overflow Flag } V = C_{n} \oplus C_{n-1}
    where CnC_n is the carry out of the MSB sign position, and Cn−1C_{n-1} is the carry into the MSB sign position. If V=1V = 1, an overflow has occurred.

6. Real Number Representation: Fixed-Point and IEEE 754 Floating-Point

6.1 Fixed-Point Representation

In fixed-point systems, a binary word of length N=I+FN = I + F allocates a fixed number of bits II to the integer magnitude and FF bits to the fractional fraction.

  • Resolution (weight of LSB): Δ=2−F\Delta = 2^{-F}.
  • Trade-off: Hardware implementation is trivial (identical to integer ALUs), but dynamic range is severely constrained.

6.2 IEEE 754 Floating-Point Architecture

To represent astronomical ranges (from sub-atomic dimensions to cosmic distances), the IEEE 754 standard defines floating-point numbers in normalized scientific form:

X=(−1)S⋅1.M⋅2E−BiasX = (-1)^S \cdot 1.M \cdot 2^{E - \text{Bias}}

CODE
   IEEE 754 Single-Precision (32-bit Float) Format
    1 bit        8 bits                           23 bits
   +------+------------------------+-------------------------------------------------------+
   |  S   |      Exponent (E)      |                     Mantissa (M)                      |
   +------+------------------------+-------------------------------------------------------+
   Bit 31  Bit 30            Bit 23 Bit 22                                            Bit 0
   (Sign)     (Biased, Bias = 127)               (Fractional significand bits)
CODE
   IEEE 754 Double-Precision (64-bit Double) Format
    1 bit        11 bits                          52 bits
   +------+-----------------------------+--------------------------------------------------+
   |  S   |        Exponent (E)         |                   Mantissa (M)                   |
   +------+-----------------------------+--------------------------------------------------+
   Bit 63  Bit 62                 Bit 52 Bit 51                                       Bit 0
   (Sign)     (Biased, Bias = 1023)              (Fractional significand bits)
CODE
+-------------------------------------------------------------------------------------------------+
|                               Special IEEE 754 Floating-Point Values                            |
+--------------------------+-----------------------+--------------------+-------------------------+
| Condition Category       | Exponent Field (E)    | Mantissa Field (M) | Numerical Meaning       |
+--------------------------+-----------------------+--------------------+-------------------------+
| Zero (+/- 0)             | All zeros (0x00)      | All zeros (M = 0)  | Exactly 0.0             |
| Subnormal Numbers        | All zeros (0x00)      | Non-zero (M != 0)  | (-1)^S * 0.M * 2^(-126) |
| Normalized Numbers       | 0x01 to 0xFE (1..254) | Any value          | (-1)^S * 1.M * 2^(E-127)|
| Infinity (+/- oo)        | All ones (0xFF)       | All zeros (M = 0)  | Division by zero        |
| Not-a-Number (NaN)       | All ones (0xFF)       | Non-zero (M != 0)  | Invalid (e.g., 0/0, sqrt(-1))|
+--------------------------+-----------------------+--------------------+-------------------------+

Step-by-Step Example: Encode Decimal −26.37510-26.375_{10} into IEEE 754 Single-Precision

  1. Determine Sign Bit: Number is negative   ⟹  S=1\implies S = 1.
  2. Convert to Pure Binary:
    • 2610=11010226_{10} = 11010_2
    • 0.37510=0.0112  ⟹  26.37510=11010.01120.375_{10} = 0.011_2 \implies 26.375_{10} = 11010.011_2
  3. Normalize to Scientific Notation:
    11010.0112=1.1010011×2411010.011_2 = 1.1010011 \times 2^4
  4. Determine Mantissa (MM):
    • The leading 1. is implied (hidden bit).
    • M=10100110000000000000000M = 10100110000000000000000 (padded with zeros to 23 bits).
  5. Compute Biased Exponent (EE):
    • Actual exponent e=4e = 4.
    • E=e+Bias=4+127=13110=100000112E = e + \text{Bias} = 4 + 127 = 131_{10} = 10000011_2.
  6. Assemble the 32-bit Word:
    • Sign (1 bit1\text{ bit}): 1
    • Exponent (8 bits8\text{ bits}): 10000011
    • Mantissa (23 bits23\text{ bits}): 10100110000000000000000
    • Word: 1 10000011 10100110000000000000000
    • Hexadecimal Representation: 0xC1D30000

7. Binary Codes for Digital Systems

Binary codes map numeric digits and alphanumeric characters into unique binary sequences tailored for specific computational, physical, or transmission environments.

7.1 Weighted and Non-Weighted Numeric Codes

In a weighted code, each bit position has an assigned numerical weight wiw_i. The decimal value of the code word b3b2b1b0b_3 b_2 b_1 b_0 is:
D=∑i=03bi⋅wiD = \sum_{i=0}^3 b_i \cdot w_i

CODE
+-------------------------------------------------------------------------------------------------+
|                                 Numeric BCD and Decimal Code Comparison                         |
+---------+--------------------+--------------------+--------------------+------------------------+
| Decimal | BCD 8421 (Weighted)| 2421 (Self-Comp.)  | 5421 (Weighted)    | Excess-3 (Non-Weighted)|
+---------+--------------------+--------------------+--------------------+------------------------+
| 0       | 0000               | 0000               | 0000               | 0011                   |
| 1       | 0001               | 0001               | 0001               | 0100                   |
| 2       | 0010               | 0010               | 0010               | 0101                   |
| 3       | 0011               | 0011               | 0011               | 0110                   |
| 4       | 0100               | 0100               | 0100               | 0111                   |
| 5       | 0101               | 1011               | 1000               | 1000                   |
| 6       | 0110               | 1100               | 1001               | 1001                   |
| 7       | 0111               | 1101               | 1010               | 1010                   |
| 8       | 1000               | 1110               | 1011               | 1011                   |
| 9       | 1001               | 1111               | 1100               | 1100                   |
+---------+--------------------+--------------------+--------------------+------------------------+

Self-Complementing Codes

A code is self-complementing if the 1's complement of the binary code word for decimal digit DD directly yields the code word for its 9's complement (9−D)(9 - D).

  • Examples: 2421 Code and Excess-3 Code.
  • Example in Excess-3: Code for 22 is 0101. Inverting all bits gives 1010, which is the Excess-3 code for 77 (9−29 - 2). This drastically simplifies decimal subtraction in ALUs.

7.2 Unit-Distance / Reflective Codes: The Gray Code

In a unit-distance code, successive numbers differ by exactly one bit. The standard binary system lacks this property (e.g., transitioning from 77 (0111) to 88 (1000) alters all 4 bits simultaneously, creating transient erroneous readouts due to mechanical and electrical delays).

CODE
          Binary Transition (0111 -> 1000)               Gray Code Transition (0100 -> 1100)
             Bit 3: 0 ----> 1                                Bit 3: 0 ----> 1  (Single bit changes)
             Bit 2: 1 ----> 0  (Spurious states occur)       Bit 2: 1 ----> 1
             Bit 1: 1 ----> 0                                Bit 1: 0 ----> 0
             Bit 0: 1 ----> 0                                Bit 0: 0 ----> 0

Algorithms for Gray Code Conversions

  1. Binary to Gray Code:
    The MSB is copied directly. Each subsequent Gray bit GiG_i is formed by XORing adjacent binary bits:
    Gn−1=Bn−1G_{n-1} = B_{n-1}
    Gi=Bi+1⊕Bi(for i=n−2,…,0)G_i = B_{i+1} \oplus B_i \quad (\text{for } i = n-2, \dots, 0)

  2. Gray Code to Binary:
    The MSB is copied directly. Each subsequent binary bit BiB_i is obtained by XORing the previously computed binary bit with the current Gray bit:
    Bn−1=Gn−1B_{n-1} = G_{n-1}
    Bi=Bi+1⊕Gi(for i=n−2,…,0)B_i = B_{i+1} \oplus G_i \quad (\text{for } i = n-2, \dots, 0)

CODE
     Binary to Gray Conversion                     Gray to Binary Conversion
       B3      B2      B1      B0                    G3      G2      G1      G0
       |       |       |       |                     |       |       |       |
       +-----+ (+)-----+ (+)---+                     |  +----+  +----+  +----+
       |      |         |                            |  |       |       |
       v      v         v                            v  v       v       v
       G3     G2        G1     G0                    B3(+)----->B2(+)-->B1(+)-->B0

7.3 Alphanumeric Codes: ASCII and Unicode

  1. ASCII (American Standard Code for Information Interchange): 7-bit code representing 128 characters (272^7), including 95 printable characters (letters, digits, punctuation) and 33 non-printable control characters (CR, LF, ACK, NUL).
  2. Extended ASCII: 8-bit code (256 characters) incorporating European accented characters and graphical box-drawing glyphs.
  3. Unicode (UTF-8, UTF-16, UTF-32): Universal variable-width encoding capable of representing over 1.1 million characters across all world languages and technical symbol sets.

8. Error Detection and Correction Codes

Electromagnetic interference, cosmic rays, and inductive motor switching can flip bits during digital transmission and memory storage.

CODE
       Transmitter                                         Receiver
   Data + Parity Bit ----------> Channel (with Noise) ----------> Parity Checker
       (Even / Odd)                    |                                |
                                     Error!                     Syndrome Evaluator
                                                                        |
                                                             Single Error Corrected!

8.1 Parity Bit Schemes (Single-Bit Error Detection)

A single redundant bit PP is appended to the data word:

  • Even Parity: PP is chosen so the total number of 1s in the code word is even:
    Peven=Dn−1⊕Dn−2⊕⋯⊕D0P_{even} = D_{n-1} \oplus D_{n-2} \oplus \dots \oplus D_0
  • Odd Parity: PP is chosen so the total number of 1s in the code word is odd:
    Podd=Dn−1⊕Dn−2⊕⋯⊕D0‾P_{odd} = \overline{D_{n-1} \oplus D_{n-2} \oplus \dots \oplus D_0}
  • Limitation: Detects all single-bit errors (and any odd number of bit errors), but is completely blind to even numbers of bit flips (2,4,62, 4, 6 errors).

8.2 Hamming Code (Single Error Correction, SEC)

Conceived by Richard Hamming, the Hamming Code detects and corrects single-bit errors dynamically by interleaving pp parity bits within mm message data bits.

The Parity Bit Equation

To locate which of the (m+p)(m + p) bits is in error, or to confirm that no error occurred, the pp parity bits must generate 2p2^p unique syndrome states:

2p≥m+p+12^p \ge m + p + 1

CODE
+-------------------------------------------------------------------------------------------------+
|                              Hamming Parity Bit Requirements Table                              |
+---------------------+-----------------------+--------------------+------------------------------+
| Data Bits (m)       | Minimum Parity Bits (p)| Total Bits (n=m+p) | Code Efficiency (m / n)      |
+---------------------+-----------------------+--------------------+------------------------------+
| 4                   | 3                     | 7 (Hamming (7,4))  | 57.1 %                       |
| 8                   | 4                     | 12 (Hamming (12,8))| 66.7 %                       |
| 16                  | 5                     | 21                 | 76.2 %                       |
| 32                  | 6                     | 38                 | 84.2 %                       |
| 64                  | 7                     | 71                 | 90.1 %                       |
+---------------------+-----------------------+--------------------+------------------------------+

Bit Placement and Syndrome Calculation

  1. Parity Bit Positioning: Parity bits are assigned strictly to positions that are powers of 2:
    P1→Bit 1,P2→Bit 2,P4→Bit 4,P8→Bit 8,…P_1 \to \text{Bit } 1, \quad P_2 \to \text{Bit } 2, \quad P_4 \to \text{Bit } 4, \quad P_8 \to \text{Bit } 8, \dots
  2. Data Bit Positioning: The remaining bit locations (3,5,6,7,9,10,…3, 5, 6, 7, 9, 10, \dots) hold data bits.
  3. Parity Coverage: Each parity bit checks all bit positions whose binary index has a 1 in the parity bit's corresponding power-of-two position:
    • P1P_1 (checks bits with LSB =1= 1): Bits 1,3,5,7,9,11,…1, 3, 5, 7, 9, 11, \dots
    • P2P_2 (checks bits with bit 1=11 = 1): Bits 2,3,6,7,10,11,…2, 3, 6, 7, 10, 11, \dots
    • P4P_4 (checks bits with bit 2=12 = 1): Bits 4,5,6,7,12,13,…4, 5, 6, 7, 12, 13, \dots
  4. Syndrome Evaluation at Receiver:
    At the receiver, the parity check equations are evaluated to produce the syndrome word S=S4S2S1S = S_4 S_2 S_1:
    • If S=000S = 000, no bit error occurred.
    • If S≠000S \ne 000, the decimal integer value of SS points directly to the erroneous bit position (e.g., S=1012=5  ⟹  Bit 5 is flippedS = 101_2 = 5 \implies \text{Bit } 5 \text{ is flipped}). Inverting that bit restores the original data word perfectly.
      """

out_dir = "content/Sem2/ECE213/unit1"
os.makedirs(out_dir, exist_ok=True)
notes_path = os.path.join(out_dir, "notes.md")
with open(notes_path, "w", encoding="utf-8") as f:
f.write(notes_content.strip() + "\n")

print(f"Written ECE213 Unit 1 notes.md to {notes_path}, total characters: {len(notes_content)}")