ECE249: Basic Electrical and Electronics Engineering

Unit 1: Fundamentals of Electrical Laws, Semiconductor Devices and its Applications

1. Fundamental Concepts of Electrical Engineering

Electrical engineering studies the behavior, transport, and practical utilization of electrical charge carriers—primarily electrons in conductors and semiconductors. Understanding electrical circuits begins with defining the fundamental physical quantities governing all electrical phenomena: charge, electric potential, current, resistance, energy, and power.

1.1 Fundamental Circuit Quantities

1. Electric Charge ($Q$):
   The intrinsic physical property of matter that causes it to experience an electrostatic force in an electromagnetic field. Quantized in units of the elementary electron charge ($e \approx 1.602 \times 10^{-19}\text{ Coulombs}$):
   $Q = \int i(t) \, dt$
2. Electric Current ($I$):
   The rate of flow of electric charge through a specified cross-sectional area per unit time. Measured in Amperes ($\text{A} = \text{Coulombs}/\text{second}$):
   $i(t) = \frac{dq(t)}{dt}$
   • Direct Current (DC): Unidirectional flow of charge with time-invariant magnitude.
   • Alternating Current (AC): Periodic bidirectional sinusoidal or periodic waveform whose magnitude and polarity oscillate cyclically.
3. Electric Potential and Voltage ($V$):
   The energy or work required to move a unit positive test charge between two distinct spatial points in an electric field. Measured in Volts ($\text{V} = \text{Joules}/\text{Coulomb}$):
   $v = \frac{dw}{dq}$
4. Resistance ($R$) and Conductance ($G$):
   The opposition that a material medium presents to the flow of electric current. For a uniform conductor with length $L$, cross-sectional area $A$, and material resistivity $\rho$:
   $R = \frac{\rho L}{A} = \frac{L}{\sigma A} \quad [\Omega]$
   where $\sigma = 1/\rho$ is electrical conductivity measured in Siemens per meter ($\text{S/m}$). Conductance $G$ is the reciprocal of resistance:
   $G = \frac{1}{R} \quad [\text{Siemens (S)} \text{ or } \mho]$
5. Electrical Power ($P$) and Energy ($W$):
   Power represents the instantaneous rate of energy expenditure or absorption:
   $P = V \cdot I = I^2 R = \frac{V^2}{R} \quad [\text{Watts (W)}]$
   Energy is the temporal integral of power:
   $W = \int_{0}^{t} P(\tau) \, d\tau \quad [\text{Joules (J)} \text{ or } \text{Kilowatt-hours (kWh)}]$
   $1\text{ kWh} = 3.6 \times 10^6\text{ Joules}$

2. Basic Circuit Laws and Network Reduction

Electrical networks consist of active energy sources (independent and dependent voltage and current sources) interconnected with passive linear circuit elements (resistors, inductors, and capacitors).

2.1 Ohm's Law and Its Physical Limits

Formulated by Georg Simon Ohm in 1827, Ohm's Law states that at constant temperature and physical dimensions, the electric current passing through an ideal conductor is directly proportional to the potential difference across its terminals:
$V = I \cdot R$

• Linear (Ohmic) Devices: Materials whose $V-I$ characteristic is a straight line through the origin (e.g., metallic resistors, carbon composition resistors).
• Non-Ohmic Devices: Materials exhibiting non-linear $V-I$ relationships where resistance varies with voltage, current, or direction (e.g., P-N junction diodes, vacuum tubes, thyristors, thermistors).

2.2 Kirchhoff's Current Law (KCL)

Kirchhoff's Current Law embodies the Principle of Conservation of Electric Charge. At any electrical node (a junction where two or more circuit branches converge), charge cannot accumulate:
$\sum_{k=1}^{n} I_k = 0$
$\sum I_{\text{entering}} = \sum I_{\text{leaving}}$

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               I1 (entering)
                    \
                     \
                      *------> I2 (leaving)
                     /  (Node)
                    /
               I3 (entering)

               Equation: I1 + I3 - I2 = 0  =>  I1 + I3 = I2

2.3 Kirchhoff's Voltage Law (KVL)

Kirchhoff's Voltage Law embodies the Principle of Conservation of Energy. The algebraic sum of all electric potential differences (voltage drops and voltage rises) around any closed loop or mesh in an electrical network is identically zero:
$\sum_{k=1}^{m} V_k = 0$
$\sum V_{\text{rises}} = \sum V_{\text{drops}}$

2.4 Resistors in Series, Parallel, and Voltage/Current Dividers

Series Combination and Voltage Divider Rule (VDR):

When $n$ resistors are connected in series, the identical current $I$ traverses each element. The equivalent resistance is the arithmetic sum:
$R_{\text{eq}} = R_1 + R_2 + \dots + R_n$
By KVL, the total applied voltage $V_S$ divides across each resistor in direct proportion to its individual resistance:
$V_{Rk} = V_S \cdot \left( \frac{R_k}{R_1 + R_2 + \dots + R_n} \right)$
For two series resistors $R_1$ and $R_2$:
$V_1 = V_S \frac{R_1}{R_1 + R_2}, \quad V_2 = V_S \frac{R_2}{R_1 + R_2}$

Parallel Combination and Current Divider Rule (CDR):

When resistors are connected across two common nodes, the identical potential difference $V$ appears across each branch. The equivalent conductance is additive:
$\frac{1}{R_{\text{eq}}} = \frac{1}{R_1} + \frac{1}{R_2} + \dots + \frac{1}{R_n}$
For two resistors in parallel:
$R_{\text{eq}} = \frac{R_1 \cdot R_2}{R_1 + R_2}$
The total input current $I_T$ divides between the branches in inverse proportion to branch resistance:
$I_1 = I_T \left( \frac{R_2}{R_1 + R_2} \right), \quad I_2 = I_T \left( \frac{R_1}{R_1 + R_2} \right)$

2.5 Systematic Circuit Analysis: Mesh and Nodal Methods

1. Mesh Current Analysis (Planar Networks):

• Assign clockwise loop currents $I_1, I_2, \dots, I_m$ to each independent planar mesh.
• Apply KVL around each mesh, accounting for mutual voltage drops across branches shared by adjacent meshes.
• Formulate the matrix equation:
  $[R_{\text{mesh}}] [I] = [V_{\text{source}}]$
  where diagonal elements $R_{ii}$ represent the sum of all resistances in mesh $i$, and off-diagonal elements $R_{ij} = -R_{\text{mutual}}$ represent shared resistances.

2. Nodal Voltage Analysis:

• Select one node as the common system ground or reference node ($V_{\text{ref}} = 0\text{ V}$).
• Assign unknown node potentials $V_1, V_2, \dots, V_{n-1}$ to all remaining essential nodes.
• Apply KCL at each non-reference node using Ohm's Law branch currents ($I = (V_{\text{node}} - V_{\text{adjacent}}) / R$).
• Solve the resulting linear system:
  $[G_{\text{nodal}}] [V] = [I_{\text{source}}]$

3. Physics of Semiconductor Materials

Semiconductor materials occupy a crucial electrical resistivity band between conductors (metals with $\rho \sim 10^{-8} \ \Omega\cdot\text{m}$) and insulators (dielectrics with $\rho > 10^{10} \ \Omega\cdot\text{m}$).

3.1 Energy Band Theory

Electrons in isolated atoms occupy discrete quantum energy states. When billions of silicon atoms pack into a diamond cubic crystal lattice, valence electron wavefunctions overlap, broadening discrete levels into continuous energy bands:

1. Valence Band ($E_V$): The highest occupied energy band filled with bonded covalent valence electrons at absolute zero ($0\text{ K}$).
2. Conduction Band ($E_C$): The lowest unoccupied band where electrons possess sufficient thermal energy to break free from covalent bonds and accelerate under an electric field.
3. Forbidden Energy Gap ($E_g$): The energy difference separating $E_V$ and $E_C$, within which no quantum electron states can exist:
   $E_g = E_C - E_V$
   • Insulators: $E_g > 5\text{ eV}$ (e.g., Diamond $\approx 5.5\text{ eV}$, $\text{SiO}_2 \approx 9\text{ eV}$).
   • Semiconductors: $E_g \approx 0.5 \text{ to } 3.0\text{ eV}$ (Silicon: $E_g = 1.12\text{ eV}$ at $300\text{ K}$; Germanium: $E_g = 0.67\text{ eV}$; Gallium Arsenide: $E_g = 1.42\text{ eV}$).
   • Conductors: Overlapping valence and conduction bands ($E_g = 0\text{ eV}$).

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     Insulator                     Semiconductor                  Conductor
  +---------------+              +---------------+              +---------------+
  |  Conduction   |              |  Conduction   |              |  Conduction   |
  |     Band      |              |     Band      |              |     Band      |
  +---------------+              +---------------+              |   (Overlaps)  |
                                                                +-------+-------+
       Eg > 5 eV                    Eg ~ 1.1 eV                 |    Valence    |
                                                                |     Band      |
  +---------------+              +---------------+              +---------------+
  |    Valence    |              |    Valence    |
  |     Band      |              |     Band      |
  +---------------+              +---------------+

3.2 Intrinsic Semiconductors and Thermal Generation

An intrinsic semiconductor is a chemically pure crystal with no significant structural defects or foreign impurity atoms (e.g., pure single-crystal silicon).

• At $T = 0\text{ K}$, all four valence electrons of each silicon atom are locked tightly in covalent bonds. The conduction band is completely empty, and the valence band is completely full. Pure silicon acts as a perfect electrical insulator.
• At room temperature ($T = 300\text{ K}$), ambient thermal energy breaks a fraction of covalent bonds, exciting electrons into the conduction band and leaving behind vacant covalent states called holes.
• Hole Concept: A hole behaves as a mobile entity possessing an effective positive charge ($+e$) and its own characteristic mobility ($\mu_p$).
• Carrier Equivalence in Intrinsic Semiconductors:
  $n = p = n_i$
  where $n$ is electron concentration, $p$ is hole concentration, and $n_i$ is the intrinsic carrier concentration.
  For Silicon at $300\text{ K}$: $n_i \approx 1.5 \times 10^{10} \ \text{cm}^{-3}$.

3.3 Extrinsic Semiconductors: Doping Principles

Extrinsic semiconductors are created by deliberately introducing precise concentrations of specific foreign impurity atoms into the silicon lattice—a process known as doping. Doping increases electrical conductivity by orders of magnitude without requiring elevated temperatures.

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+-----------------------------------------------------------------------------------------+
| Characteristic          | N-Type Semiconductor            | P-Type Semiconductor        |
+-------------------------+---------------------------------+-----------------------------+
| Dopant Type             | Pentavalent (Group V)           | Trivalent (Group III)       |
| Common Impurities       | Phosphorus (P), Arsenic (As),   | Boron (B), Aluminum (Al),   |
|                         | Antimony (Sb)                   | Gallium (Ga), Indium (In)   |
| Role of Dopant          | Donor atoms ($N_D$)             | Acceptor atoms ($N_A$)      |
| Extra Energy Level      | Donor level $E_D$ near $E_C$    | Acceptor level $E_A$ near $E_V$ |
| Majority Carriers       | Electrons ($n \approx N_D$)     | Holes ($p \approx N_A$)     |
| Minority Carriers       | Holes ($p = n_i^2 / N_D$)       | Electrons ($n = n_i^2 / N_A$)|
| Net Electrical Charge   | Electrically Neutral overall    | Electrically Neutral overall|
+-----------------------------------------------------------------------------------------+

Mass-Action Law:

In any non-degenerate semiconductor at thermal equilibrium:
$n \cdot p = n_i^2$
This fundamental relation dictates that increasing majority carrier concentration through doping inevitably suppresses the minority carrier population via accelerated recombination.

4. The P-N Junction Diode

When a p-type semiconductor and an n-type semiconductor are joined metallurgically within a single continuous crystal lattice, a P-N junction is formed.

4.1 Formation of the Depletion Region and Built-In Potential

1. Diffusion Current: Due to steep carrier concentration gradients across the metallurgical interface, majority electrons diffuse from the n-side into the p-side, while majority holes diffuse from the p-side into the n-side.
2. Uncompensated Space Charge: As electrons depart the n-region, they leave behind unneutralized, positively ionized donor impurity cores ($\text{P}^+$) locked in the lattice. Similarly, diffusing holes leave behind unneutralized negatively ionized acceptor cores ($\text{B}^-$) on the p-side.
3. Depletion Region (Space Charge Layer): A narrow region devoid of mobile charge carriers forms across the metallurgical interface, populated exclusively by fixed ionic charges.
4. Built-in Electric Field ($\vec{E}$): The spatial separation of positive donor ions on the n-side and negative acceptor ions on the p-side creates an internal electric field directed from n to p. This field produces a drift current opposing diffusion.
5. Thermal Equilibrium: Equilibrium is reached when the drift current driven by the internal electric field exactly cancels the diffusion current:
   $I_{\text{drift}} + I_{\text{diffusion}} = 0$
   The resulting potential barrier across the depletion layer is the Built-in Potential ($V_{bi}$):
   $V_{bi} = V_T \ln\left( \frac{N_A \cdot N_D}{n_i^2} \right)$
   where $V_T = \frac{k_B T}{q}$ is the thermal voltage ($\approx 25.9\text{ mV}$ at $300\text{ K}$).
   • Silicon: $V_{bi} \approx 0.7\text{ V}$ to $0.8\text{ V}$
   • Germanium: $V_{bi} \approx 0.2\text{ V}$ to $0.3\text{ V}$

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            P-Region               Depletion Region               N-Region
     +---------------------+-----------------------------+---------------------+
     | Holes (Majority)    | Fixed Acceptors | Fixed Donors| Electrons (Majority)|
     |                     |      (-)        |     (+)     |                     |
     |         p           |      (-)        |     (+)     |          n          |
     |                     |      (-)        |     (+)     |                     |
     +---------------------+-----------------------------+---------------------+
                                       <------
                                Built-in Field E (n to p)
                           Barrier Potential Vbi ~ 0.7 V

4.2 Biasing the P-N Junction Diode

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                     P-N Junction Biasing Schemes
                                  |
         +------------------------+------------------------+
         |                                                 |
    Forward Bias                                     Reverse Bias
    (P connected to +, N connected to -)             (P connected to -, N connected to +)
    - Applied V opposes Vbi                          - Applied V reinforces Vbi
    - Depletion width narrows                        - Depletion width widens
    - Exponential conduction above 0.7 V             - Negligible reverse saturation current Is

1. Forward Bias ($V_D > 0$):
   • The positive external terminal connects to the p-type anode and the negative terminal to the n-type cathode.
   • The applied external electric field directly opposes the built-in barrier field, lowering the potential barrier to $(V_{bi} - V_D)$.
   • The depletion layer width narrows substantially.
   • Once $V_D$ exceeds the threshold or knee voltage ($V_K \approx 0.7\text{ V}$ for Si, $0.3\text{ V}$ for Ge), majority carriers overcome the barrier, resulting in large forward current flow.
2. Reverse Bias ($V_D < 0$):
   • The negative terminal connects to the p-side and the positive terminal to the n-side.
   • The applied field aids the built-in field, expanding the barrier height to $(V_{bi} + |V_R|)$ and widening the depletion region.
   • Majority carrier diffusion drops to zero.
   • A minute reverse saturation current ($I_S$) flows, carried by minority carriers (electrons thermally generated in the p-region and holes in the n-region) swept across the junction by the field. $I_S$ is typically $10^{-12} \text{ A}$ (picoamperes) for silicon and is largely independent of reverse voltage until breakdown.

4.3 The Shockley Diode Equation and Resistance Definitions

The current-voltage relationship of an ideal P-N junction diode under forward and reverse bias is governed by the Shockley Diode Equation:
$I_D = I_S \left( e^{\frac{V_D}{\eta V_T}} - 1 \right)$
where:

• $I_D$ = Diode terminal current
• $I_S$ = Reverse saturation current
• $V_D$ = Terminal voltage across the P-N junction
• $\eta$ = Ideality factor ($\eta \approx 1$ for Ge; $\eta \approx 1 \text{ to } 2$ for Si depending on current level)
• $V_T$ = Thermal voltage ($V_T = k_B T / q \approx 26\text{ mV}$ at room temperature)

Diode Resistances:

1. DC (Static) Resistance ($R_{\text{DC}}$):
   The ratio of DC voltage to DC current at a specified operating point:
   $R_{\text{DC}} = \frac{V_D}{I_D}$
2. AC (Dynamic) Resistance ($r_d$):
   The reciprocal of the derivative of the $I-V$ characteristic at the Q-point:
   $r_d = \left( \frac{dI_D}{dV_D} \right)^{-1} = \frac{\eta V_T}{I_D + I_S} \approx \frac{\eta V_T}{I_D} = \frac{26\text{ mV}}{I_D\text{ (mA)}} \quad (\text{for } \eta = 1)$

5. Diode Applications: Rectifier Circuits and Power Supplies

Rectification is the conversion of bidirectional alternating current (AC) into unidirectional direct current (DC).

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   AC Mains 230V, 50Hz
          |
          v
   +---------------+      +---------------+      +---------------+      +---------------+
   | Step-Down     |----->| Diode         |----->| Smoothing     |----->| Voltage       |-----> Stable DC
   | Transformer   |      | Rectifier     |      | Filter (C)    |      | Regulator (IC)|       Output
   +---------------+      +---------------+      +---------------+      +---------------+

5.1 Half-Wave Rectifier (HWR)

A Half-Wave Rectifier utilizes a single diode connected in series with a load resistor $R_L$ driven by an AC transformer secondary voltage:
$v_s(t) = V_m \sin(\omega t)$

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          Transformer
             ||
       *-----+||+-----[ Diode D1 ]------+
             ||                         |
      230V   ||                       +---+
      50Hz   ||                       |   | RL  V_out
             ||                       |   |
       *-----+||+-----------------------+
             ||                         |
                                       GND

Mathematical Analysis of HWR:

• Positive Half-Cycle ($0 \le \omega t \le \pi$): Diode is forward biased (acting as an ideal closed switch). $v_o(t) = V_m \sin(\omega t)$.
• Negative Half-Cycle ($\pi \le \omega t \le 2\pi$): Diode is reverse biased (open switch). $v_o(t) = 0$.

1. DC (Average) Output Voltage ($V_{\text{dc}}$):
   $V_{\text{dc}} = \frac{1}{2\pi} \int_{0}^{\pi} V_m \sin(\omega t) \, d(\omega t) = \frac{V_m}{\pi} \approx 0.318 V_m$
2. RMS Output Voltage ($V_{\text{rms}}$):
   $V_{\text{rms}} = \sqrt{\frac{1}{2\pi} \int_{0}^{\pi} [V_m \sin(\omega t)]^2 \, d(\omega t)} = \frac{V_m}{2} = 0.5 V_m$
3. Rectification Efficiency ($\eta$):
   $\eta = \frac{P_{\text{dc}}}{P_{\text{ac}}} = \frac{(I_{\text{dc}})^2 R_L}{(I_{\text{rms}})^2 (r_f + R_L)} \approx \frac{(I_m/\pi)^2 R_L}{(I_m/2)^2 R_L} = \frac{4}{\pi^2} \approx 40.6\%$
4. Ripple Factor ($r$):
   $r = \frac{V_{\text{ac,rms}}}{V_{\text{dc}}} = \sqrt{\left(\frac{V_{\text{rms}}}{V_{\text{dc}}}\right)^2 - 1} = \sqrt{\left(\frac{V_m/2}{V_m/\pi}\right)^2 - 1} = \sqrt{\frac{\pi^2}{4} - 1} \approx 1.21$
5. Peak Inverse Voltage (PIV):
   The maximum reverse voltage the diode must withstand during the negative half-cycle:
   $\text{PIV} = V_m$
6. Output Fundamental Ripple Frequency:
   $f_{\text{ripple}} = f_{\text{in}} = 50\text{ Hz}$

5.2 Full-Wave Rectifier (FWR)

1. Center-Tapped Full-Wave Rectifier:

Employs a center-tapped transformer secondary winding producing two anti-phase sinusoidal voltages ($v_1 = V_m \sin(\omega t)$ and $v_2 = -V_m \sin(\omega t)$) and two diodes ($D_1$ and $D_2$).

• Positive half-cycle: $D_1$ conducts; $D_2$ is reverse biased. Current flows downward through $R_L$.
• Negative half-cycle: $D_2$ conducts; $D_1$ is reverse biased. Current continues flowing downward through $R_L$.
• Peak Inverse Voltage (PIV):
  $\text{PIV} = 2V_m$

2. Full-Wave Bridge Rectifier:

Utilizes four diodes ($D_1, D_2, D_3, D_4$) arranged in a bridge loop across a standard secondary winding.

• Positive half-cycle: $D_1$ and $D_2$ conduct in series with $R_L$, while $D_3$ and $D_4$ are reverse biased.
• Negative half-cycle: $D_3$ and $D_4$ conduct in series with $R_L$, while $D_1$ and $D_2$ are reverse biased.
• Current traverses the load in the identical direction during both half-cycles.
• Peak Inverse Voltage (PIV):
  $\text{PIV} = V_m$
  (Taking non-ideal diode drop into account: $V_o = V_m - 2V_D = V_m - 1.4\text{ V}$).

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                     Bridge Rectifier Circuit
                   +-----------[ D1 ]-----------+
                   |                            |
       *-----+||+--+             +--------------*----[+]
             ||    |             |              |
      230V   ||    +---[ D4 ]----+              |
      50Hz   ||                  |              |
             ||                  |            +---+
       *-----+||+--+             |            |   | RL
                   |             |            |   |
                   +---[ D3 ]----+            +---+
                   |                            |
                   +-----------[ D2 ]-----------*----[-]

Mathematical Metrics of Full-Wave Rectifiers:

1. DC Output Voltage ($V_{\text{dc}}$):
   $V_{\text{dc}} = \frac{2V_m}{\pi} \approx 0.636 V_m$
2. RMS Output Voltage ($V_{\text{rms}}$):
   $V_{\text{rms}} = \frac{V_m}{\sqrt{2}} \approx 0.707 V_m$
3. Maximum Theoretical Efficiency ($\eta$):
   $\eta = \frac{8}{\pi^2} \approx 81.2\%$
4. Ripple Factor ($r$):
   $r = \sqrt{\left(\frac{V_{\text{rms}}}{V_{\text{dc}}}\right)^2 - 1} = \sqrt{\left(\frac{V_m/\sqrt{2}}{2V_m/\pi}\right)^2 - 1} = \sqrt{\frac{\pi^2}{8} - 1} \approx 0.482$
5. Output Fundamental Ripple Frequency:
   $f_{\text{ripple}} = 2 f_{\text{in}} = 100\text{ Hz}$

5.3 Comparison of Rectifier Topologies

5.4 Smoothing Filter Circuits

Unfiltered pulsating DC is unsuitable for powering electronic circuits. Smoothing filters reduce the AC ripple component while preserving the average DC level:

1. Shunt Capacitor Filter ($C$-Filter):
   A high-value electrolytic capacitor $C$ placed in parallel with $R_L$. The capacitor charges rapidly to $V_m$ during the diode conduction peak and discharges slowly through $R_L$ when diode voltage drops.
   • Ripple factor for Full-Wave Rectifier with shunt $C$:
     $r = \frac{1}{4\sqrt{3} f C R_L}$
     $V_{\text{dc}} \approx V_m - \frac{V_r}{2} = V_m - \frac{I_{\text{dc}}}{4 f C}$
2. Series Inductor Filter ($L$-Filter):
   An inductor placed in series with the load. By Faraday's Law ($v_L = L \frac{di}{dt}$), the inductor opposes instantaneous fluctuations in current. Effective for heavy loads (low $R_L$).
3. $\pi$-Filter (C-L-C Filter):
   Combines two shunt capacitors with an intermediate series inductor, achieving extremely low ripple factor ($r \approx \frac{\sqrt{2}}{8\omega^3 C_1 C_2 L R_L}$).

6. Special Purpose Semiconductor Diodes

Beyond standard power rectification, specialized dopant engineering produces diodes with tailored physical properties:

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+-----------------------------------------------------------------------------------------+
| Diode Type        | Symbol / Junction Character | Primary Operational Mechanism         |
+-------------------+-----------------------------+---------------------------------------+
| Zener Diode       | Heavily doped P-N junction  | Controlled reverse breakdown          |
|                   |                             | (Zener and Avalanche tunneling)       |
| LED               | Direct bandgap (GaAs, GaP)  | Spontaneous radiative recombination   |
| Photodiode        | Reverse-biased P-N junction | Optoelectronic electron-hole          |
|                   |                             | pair generation via photon absorption |
| Varactor Diode    | Variable reverse bias       | Voltage-dependent junction depletion  |
|                   |                             | capacitance $C_j(V_R)$                |
+-----------------------------------------------------------------------------------------+

6.1 Zener Diode and Breakdown Mechanisms

A Zener diode is fabricated with exceptionally heavy doping on both p and n sides. Under forward bias, it behaves as a normal silicon diode. Under reverse bias, it operates safely in the breakdown region, maintaining an almost constant voltage $V_Z$ across an extensive range of reverse currents ($I_{ZK} \le I_Z \le I_{ZM}$).

Breakdown Mechanisms:

1. Zener Breakdown ($V_Z < 6\text{ V}$):
   • Due to heavy doping, the depletion width is ultra-narrow ($< 10\text{ nm}$).
   • Even a modest reverse voltage generates an intense electric field ($> 3 \times 10^5\text{ V/cm}$).
   • This field exerts strong force on valence electrons, ripping them from covalent bonds and causing direct quantum mechanical tunneling into the conduction band.
   • Temperature Coefficient: Negative ($\frac{dV_Z}{dT} < 0$). Increased temperature narrows the forbidden gap, facilitating tunneling at lower voltages.
2. Avalanche Breakdown ($V_Z > 6\text{ V}$):
   • Occurs in lightly doped junctions with wider depletion layers.
   • Minority carriers traversing the junction are accelerated by the field to high kinetic energies.
   • Collisions with lattice atoms knock valence electrons free (impact ionization), which in turn accelerate and produce more carriers, causing an avalanche multiplication of current.
   • Temperature Coefficient: Positive ($\frac{dV_Z}{dT} > 0$). Thermal lattice vibrations scatter carriers, requiring higher reverse voltages to reach ionization energy.

6.2 Zener Diode as a Shunt Voltage Regulator

The Zener diode maintains a constant output voltage $V_o = V_Z$ despite variations in source input voltage $V_S$ (Line Regulation) or load current $I_L$ (Load Regulation).

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                      Rs
            +-------/\/\/\-------*-------------+-----[+]
            |                    |             |
           +|+                   |            +---+
      Vs   ---                 [ Zener ]      |   | RL   Vo = Vz
      (DC)  |                  [  Vz   ]      |   |
           -|-                   |            +---+
            |                    |             |
            +--------------------*-------------+-----[-]

Circuit Governing Equations:

1. Input loop voltage:
   $V_S = I_S R_S + V_Z \implies I_S = \frac{V_S - V_Z}{R_S}$
2. Kirchhoff's Current Law at output node:
   $I_S = I_Z + I_L \implies I_Z = I_S - I_L$
3. Load current:
   $I_L = \frac{V_Z}{R_L}$
4. Design constraints for safe regulation:
   • Minimum Zener current to ensure the diode stays in breakdown:
     $I_Z \ge I_{ZK} \implies R_{S,\max} = \frac{V_{S,\min} - V_Z}{I_{L,\max} + I_{ZK}}$
   • Maximum Zener current to prevent exceeding maximum power dissipation ($P_{ZM} = V_Z I_{ZM}$):
     $R_{S,\min} = \frac{V_{S,\max} - V_Z}{I_{L,\min} + I_{ZM}}$

6.3 Light-Emitting Diode (LED) and Photodiode

1. Light-Emitting Diode (LED):
   • Fabricated from direct bandgap semiconductors (such as Gallium Arsenide, GaAs; Gallium Nitride, GaN) where conduction band minima and valence band maxima align in momentum space ($k$-space).
   • Under forward bias, injected electrons and holes recombine radiatively across the bandgap, releasing excess energy directly as photons of light:
     $\lambda = \frac{h c}{E_g} \approx \frac{1240}{E_g\text{ (eV)}} \quad [\text{nm}]$
   • (Indirect bandgap semiconductors like silicon and germanium release energy primarily as lattice heat/phonons, making them unsuitable for LEDs).
2. Photodiode:
   • Operated under reverse bias with an optical window exposing the depletion region.
   • Incident photons with energy $h\nu \ge E_g$ break covalent bonds, generating electron-hole pairs within the depletion layer.
   • The built-in electric field sweeps electrons to the n-side and holes to the p-side, producing a reverse photocurrent $I_\lambda$ directly proportional to optical illumination intensity.

7. Bipolar Junction Transistors (BJT)

The Bipolar Junction Transistor is a three-terminal, three-layer semiconductor device capable of current amplification, signal processing, and high-speed electronic switching.

CODECopy Code
            NPN Transistor                              PNP Transistor
    Collector (C)      Base (B)             Collector (C)      Base (B)
        (N)              (P)                    (P)              (N)
    +-----------+--------------------+      +-----------+--------------------+
    | Moderate  | Ultra-thin, Light  |      | Moderate  | Ultra-thin, Light  |
    +-----------+--------------------+      +-----------+--------------------+
        (N)                                     (P)
    | Heavily   |                           | Heavily   |
    |  Doped    |                           |  Doped    |
    +-----------+                           +-----------+
     Emitter (E)                             Emitter (E)

7.1 Physical Structure and Terminal Doping Profile

1. Emitter (E): Heavily doped ($N_D^{++} \approx 10^{19}\text{ cm}^{-3}$) to inject a massive density of majority carriers into the base. Moderate physical size.
2. Base (B): Lightly doped ($N_A \approx 10^{16}\text{ cm}^{-3}$) and engineered to be physically ultra-thin ($W_B \ll L_n$, typical width $< 1 \ \mu\text{m}$) so that nearly all injected carriers traverse it without recombining.
3. Collector (C): Moderately doped to withstand reverse bias breakdown voltages. Physically the largest region to facilitate thermal heat dissipation generated by high collector-base voltages.

7.2 Transistor Configurations and Current Relations

By Kirchhoff's Current Law:
$I_E = I_B + I_C$

Common-Base Configuration (CB):

• Input applied across Emitter-Base; output taken across Collector-Base.
• Common-Base Current Gain ($\alpha$):
  $\alpha = \frac{I_C}{I_E} \quad (\text{typically } 0.95 \text{ to } 0.998)$
  $I_C = \alpha I_E + I_{CBO}$
  where $I_{CBO}$ is the collector-to-base reverse leakage current with emitter open.

Common-Emitter Configuration (CE):

• Input applied to Base; output taken from Collector. Most widely used configuration providing high current gain and high voltage gain.
• Common-Emitter Current Gain ($\beta$ or $h_{FE}$):
  $\beta = \frac{I_C}{I_B} \quad (\text{typically } 50 \text{ to } 300)$
  Mathematical relationship between $\alpha$ and $\beta$:
  $\beta = \frac{\alpha}{1 - \alpha}, \quad \alpha = \frac{\beta}{\beta + 1}$
  $I_C = \beta I_B + (\beta + 1) I_{CBO} = \beta I_B + I_{CEO}$

7.3 Common-Emitter (CE) Input and Output Characteristics

CODECopy Code
        Output Characteristics (IC vs VCE)
     IC (mA)
       ^
       |       Active Region
       |------------------------ IB = 40 uA
       |------------------------ IB = 30 uA
       |------------------------ IB = 20 uA
       |------------------------ IB = 10 uA
       |________________________ IB = 0  (Cut-off Region)
       +---------------------------------------------> VCE (V)
       |<->|
     Saturation

Operational Regions of a BJT:

7.4 DC Load Line and Operating Point (Q-Point)

For a common-emitter circuit biased by supply voltage $V_{CC}$ through collector load resistor $R_C$:
Apply KVL around the output collector loop:
$V_{CC} - I_C R_C - V_{CE} = 0 \implies I_C = -\frac{1}{R_C} V_{CE} + \frac{V_{CC}}{R_C}$
This linear relationship defines the DC Load Line:

• Y-intercept (Saturation limit): Set $V_{CE} = 0 \implies I_{C(\text{sat})} = \frac{V_{CC}}{R_C}$.
• X-intercept (Cut-off limit): Set $I_C = 0 \implies V_{CE(\text{cutoff})} = V_{CC}$.
• Quiescent Point (Q-Point): The intersection of the DC load line with the transistor output characteristic curve for a specific base current $I_B$. The Q-point coordinates $(V_{CEQ}, I_{CQ})$ define the steady-state DC operating point. For maximum symmetrical undistorted AC voltage swing, the Q-point should be placed in the center of the active region:
  $V_{CEQ} = \frac{V_{CC}}{2}, \quad I_{CQ} = \frac{V_{CC}}{2 R_C}$

8. Solved Engineering Problems and Analytical Calculations

Problem 1: Unloaded and Loaded Zener Voltage Regulator

Problem Statement:
A 12V Zener diode is used in a shunt voltage regulator circuit. The DC input voltage $V_S$ varies between $18\text{ V}$ and $24\text{ V}$. The series resistor is $R_S = 220 \ \Omega$. The Zener knee current is $I_{ZK} = 5\text{ mA}$, and the maximum rated power is $P_{ZM} = 1.2\text{ W}$.

1. Calculate the maximum safe Zener current $I_{ZM}$.
2. Determine the range of Zener current when no load is connected ($R_L = \infty$).
3. If a load resistor $R_L = 470 \ \Omega$ is connected across the output, determine $I_L$, $I_S$, and $I_Z$ at the minimum input voltage $V_S = 18\text{ V}$. Verify if regulation is maintained.

Analytical Solution:

1. Maximum Zener Current ($I_{ZM}$):
   $I_{ZM} = \frac{P_{ZM}}{V_Z} = \frac{1.2\text{ W}}{12\text{ V}} = 0.1\text{ A} = 100\text{ mA}$
2. Unloaded Zener Currents ($I_L = 0 \implies I_Z = I_S$):
   • At $V_{S,\min} = 18\text{ V}$:
     $I_{Z,\min} = \frac{18\text{ V} - 12\text{ V}}{220 \ \Omega} = \frac{6\text{ V}}{220 \ \Omega} \approx 27.27\text{ mA}$
   • At $V_{S,\max} = 24\text{ V}$:
     $I_{Z,\max} = \frac{24\text{ V} - 12\text{ V}}{220 \ \Omega} = \frac{12\text{ V}}{220 \ \Omega} \approx 54.55\text{ mA}$
     Since $54.55\text{ mA} < I_{ZM} = 100\text{ mA}$, the Zener operates safely without overheating.
3. Loaded Conditions at $V_S = 18\text{ V}$ with $R_L = 470 \ \Omega$:
   • Assuming regulation holds, output voltage is clamped at $V_o = V_Z = 12\text{ V}$:
     $I_L = \frac{V_Z}{R_L} = \frac{12\text{ V}}{470 \ \Omega} \approx 25.53\text{ mA}$
   • Total source current:
     $I_S = \frac{V_S - V_Z}{R_S} = \frac{18\text{ V} - 12\text{ V}}{220 \ \Omega} \approx 27.27\text{ mA}$
   • Resulting Zener current:
     $I_Z = I_S - I_L = 27.27\text{ mA} - 25.53\text{ mA} = 1.74\text{ mA}$
   • Verification: Notice that $I_Z = 1.74\text{ mA} < I_{ZK} = 5\text{ mA}$.
     Because the resulting Zener current drops below the knee threshold, the diode drops out of the breakdown region. Consequently, full regulation is lost under this worst-case minimum input voltage and heavy load combination. To maintain regulation, $R_S$ must be decreased to supply at least $I_S = I_L + I_{ZK} = 25.53 + 5 = 30.53\text{ mA}$.

Problem 2: Full-Wave Bridge Rectifier Performance Analysis

Problem Statement:
A bridge rectifier is fed by a 230V, 50Hz AC mains line via a step-down transformer with a turns ratio $N_p : N_s = 10 : 1$. The load resistance is $R_L = 500 \ \Omega$. Assume ideal diodes (forward drop $V_D = 0$).
Calculate:

1. Peak secondary voltage $V_m$.
2. DC output voltage $V_{\text{dc}}$ and DC load current $I_{\text{dc}}$.
3. RMS output voltage $V_{\text{rms}}$ and ripple factor $r$.
4. Total DC power delivered to the load and rectification efficiency $\eta$.
5. Minimum required Peak Inverse Voltage (PIV) rating for each diode.

Analytical Solution:

1. Transformer Secondary Voltages:
   • RMS secondary voltage:
     $V_{s,\text{rms}} = \frac{V_{\text{primary}}}{10} = \frac{230\text{ V}}{10} = 23\text{ V}$
   • Peak secondary voltage:
     $V_m = \sqrt{2} \cdot V_{s,\text{rms}} = \sqrt{2} \cdot 23\text{ V} \approx 32.53\text{ V}$
2. DC Output Values:
   $V_{\text{dc}} = \frac{2 V_m}{\pi} = \frac{2 \cdot 32.53\text{ V}}{\pi} \approx 20.71\text{ V}$
   $I_{\text{dc}} = \frac{V_{\text{dc}}}{R_L} = \frac{20.71\text{ V}}{500 \ \Omega} \approx 0.0414\text{ A} = 41.4\text{ mA}$
3. RMS Output Voltage and Ripple Factor:
   $V_{\text{rms}} = \frac{V_m}{\sqrt{2}} = \frac{32.53\text{ V}}{\sqrt{2}} = 23\text{ V}$
   $r = \sqrt{\left(\frac{V_{\text{rms}}}{V_{\text{dc}}}\right)^2 - 1} = \sqrt{\left(\frac{23}{20.71}\right)^2 - 1} = \sqrt{(1.1105)^2 - 1} \approx 0.483$
4. Power and Efficiency:
   $P_{\text{dc}} = V_{\text{dc}} \cdot I_{\text{dc}} = 20.71\text{ V} \times 0.0414\text{ A} \approx 0.857\text{ W}$
   $P_{\text{ac}} = \frac{(V_{\text{rms}})^2}{R_L} = \frac{(23\text{ V})^2}{500 \ \Omega} \approx 1.058\text{ W}$
   $\eta = \frac{P_{\text{dc}}}{P_{\text{ac}}} = \frac{0.857}{1.058} \approx 81.0\% \quad (\text{ideal limit is } 81.2\%)$
5. Peak Inverse Voltage (PIV):
   $\text{PIV} = V_m = 32.53\text{ V}$

9. Summary and Revision Guide

• Circuit Theorems: Ohm's Law ($V=IR$), KCL (conservation of charge, $\sum I = 0$ at a node), KVL (conservation of energy, $\sum V = 0$ around a loop).
• Network Reduction:
  • Series resistors: $R_{\text{eq}} = \sum R_i$; Voltage divider: $V_1 = V_S \frac{R_1}{R_1+R_2}$.
  • Parallel resistors: $R_{\text{eq}} = \frac{R_1 R_2}{R_1 + R_2}$; Current divider: $I_1 = I_T \frac{R_2}{R_1+R_2}$.
• Semiconductor Physics:
  • Silicon bandgap $E_g = 1.12\text{ eV}$, Germanium $E_g = 0.67\text{ eV}$.
  • Intrinsic: $n = p = n_i$. Extrinsic: N-type (Group V donors, electrons majority), P-type (Group III acceptors, holes majority). Mass-action law: $n \cdot p = n_i^2$.
• P-N Junction: Built-in potential $V_{bi} = V_T \ln(N_A N_D / n_i^2) \approx 0.7\text{ V}$ (Si). Forward bias reduces depletion width and enables exponential conduction; reverse bias widens depletion width with minimal leakage current $I_S$.
• Rectification:
  • HWR: $\eta = 40.6\%$, $r = 1.21$, $\text{PIV} = V_m$, $f_{\text{out}} = f_{\text{in}}$.
  • FWR (Center-tapped): $\eta = 81.2\%$, $r = 0.482$, $\text{PIV} = 2V_m$, $f_{\text{out}} = 2f_{\text{in}}$.
  • FWR (Bridge): $\eta = 81.2\%$, $r = 0.482$, $\text{PIV} = V_m$, $f_{\text{out}} = 2f_{\text{in}}$.
• Zener Diode: Operates in controlled reverse breakdown. Zener breakdown ($V_Z < 6\text{ V}$, quantum tunneling, negative temp coefficient); Avalanche breakdown ($V_Z > 6\text{ V}$, impact ionization, positive temp coefficient). Used as a shunt voltage regulator.
• BJT Operation: $I_E = I_B + I_C$. Current gain $\alpha = I_C/I_E$, $\beta = I_C/I_B$, $\beta = \frac{\alpha}{1-\alpha}$. Operating regions: Active (EBJ forward, CBJ reverse), Saturation (both forward), Cut-off (both reverse).