Unit 1: Introduction to Digital Systems and HDLs

1. Executive Summary & Architectural Framework

Computer Organization and Design bridges abstract software logic with physical silicon hardware. At the lowest computational level, digital systems comprise registers, arithmetic execution units, and control automata coordinated by micro-operations.

1. Register Transfer Language (RTL): A rigorous symbolic notation defining micro-operations, data transfers between processor registers, common bus arbitration, and memory interactions.
2. Hardware Description Languages (HDLs): Specialized hardware modeling languages (primarily Verilog and VHDL) that describe concurrent electrical circuits, supporting a rigorous design flow from behavioral simulation to logic synthesis and physical silicon fabrication.

2. Register Transfer Language (RTL) & Bus Architecture

A. Register Transfer Notation & Control Functions

A Register is a group of binary flip-flops with parallel load capability that stores digital words (e.g., Program Counter PC, Memory Address Register AR, Accumulator AC, Data Register DR).

• Basic Transfer: $R2 \leftarrow R1$ denotes copying the content of register $R1$ into register $R2$ without altering $R1$.
• Conditional Control Transfer: Transfer execution is governed by a boolean control condition $P$:
  $P: \quad R2 \leftarrow R1$
  Symbolizes: If control condition $P = 1$, then content of $R1$ is loaded into $R2$ synchronously at the next rising clock edge.

CODECopy Code
   Control Unit                Datapath
  +------------+            +------------+
  | Clock Pulse| ---------> |  Flip-Flop |
  |   P = 1    | ---------> | Load (LD)  |
  +------------+            +------------+
                              R2 <-- R1

B. Common Bus Architecture

Routing dedicated point-to-point physical wires between every pair of registers requires $O(N^2)$ interconnects, which causes physical silicon routing congestion. A Common Bus System provides a shared communication channel:

1. Multiplexer-Based Bus:
   • For $K$ registers of $N$ bits each, $N$ multiplexers of size $K \times 1$ are utilized.
   • The selection inputs $S_1, S_0$ choose which register drives its binary word onto the common bus lines.
   • To construct a bus for four 4-bit registers: four $4 \times 1$ MUXes are used with 2 select lines.
2. Three-State Bus Buffers:
   • Uses tri-state buffers possessing three states: Logic 0, Logic 1, and High-Impedance (Hi-Z).
   • Hi-Z behaves like an open electrical circuit, disconnecting the register output from the bus line.
   • A decoder ensures that only one register's tri-state enable line ($E$) is asserted at any clock cycle.

C. Memory Transfers: Read and Write

The internal Random Access Memory (RAM) unit communicates via the Memory Address Register ($AR$) and Data Register ($DR$):

• Memory Read Operation:
  $Read: \quad DR \leftarrow M[AR]$
  Data from memory word selected by address $AR$ is transferred into register $DR$.
• Memory Write Operation:
  $Write: \quad M[AR] \leftarrow R1$
  Content of register $R1$ is stored into memory location addressed by $AR$.

3. Micro-operations

A micro-operation is an elementary digital operation performed on data stored inside one or more registers during a single clock cycle.

A. Arithmetic Micro-operations

Basic arithmetic encompasses addition, subtraction, increment, decrement, and complement:

CODECopy Code
Binary Adder-Subtractor Circuit:
- Controlled by mode input M:
  - If M = 0: B inputs pass un-inverted (B XOR 0 = B), carry-in C0 = 0 -> Performs Addition: A + B
  - If M = 1: B inputs are inverted (B XOR 1 = B'), carry-in C0 = 1 -> Performs Subtraction: A + B' + 1

B. Logic Micro-operations

Logic micro-operations treat each bit in the register independently as a binary variable (bitwise operations):

1. Selective-Set: Forces specific bits to $1$ without altering others (using bitwise OR with a mask: $A \leftarrow A \lor B$).
2. Selective-Clear: Forces specific bits to $0$ without altering others (using $A \leftarrow A \land \overline{B}$).
3. Selective-Complement: Inverts specific target bits (using bitwise XOR with a mask: $A \leftarrow A \oplus B$).
4. Masking (Clear to 0): Retains bits where mask is 1 and clears bits where mask is 0 ($A \leftarrow A \land B$).

C. Shift Micro-operations

Shift micro-operations relocate bits laterally across register bit-positions:

1. Logical Shift: Inserts $0$ into the vacated serial input position:
   • Logical Shift Left (shl): $R \leftarrow \text{shl } R$ (equivalent to multiplying unsigned binary by 2, if no overflow).
   • Logical Shift Right (shr): $R \leftarrow \text{shr } R$ (equivalent to integer division by 2).
2. Circular Shift (Rotate): Circulates bits in a continuous loop without bit loss:
   • Circular Shift Left (cil): Bit from MSB wraps around into LSB.
   • Circular Shift Right (cir): Bit from LSB wraps around into MSB.
3. Arithmetic Shift: Multiplies or divides a signed binary number in 2's complement:
   • Arithmetic Shift Right (ashr): Shifts bits rightward while preserving the sign bit (MSB): $R_{n-1}$ is replicated into $R_{n-2}$, keeping sign intact.
   • Arithmetic Shift Left (ashl): Shifts left and inserts 0 into LSB.
   • Arithmetic Overflow: Occurs if shifting changes the sign bit. Monitored by the overflow flip-flop $V$:
     $V = R_{n-1} \oplus R_{n-2}$

4. Booth's Multiplication Algorithm

Booth's Algorithm multiplies two signed binary integers in 2's complement representation in $O(N)$ cycles, treating strings of consecutive 1s efficiently.

Operational Mechanics:

• Maintain Multiplicand ($M$), Accumulator ($A$, initialized to 0), Multiplier ($Q$), and an extra flip-flop ($Q_{-1}$, initialized to 0).
• In each cycle, examine the two lowest bits: $Q_0$ and $Q_{-1}$:

• After the arithmetic step (if any), perform an Arithmetic Right Shift across the combined register block $[A, Q, Q_{-1}]$.
• Repeat for $N$ clock cycles (where $N$ is the bit-width of operands).

5. Introduction to Hardware Description Languages (HDLs)

A. History & Evolution

• Prior to HDLs, digital circuits were manually drafted using schematic capture and Karnaugh maps. As transistor counts exploded into VLSI and ULSI, schematic drafting became intractable.
• VHDL (Very High Speed Integrated Circuit HDL): Developed in the 1980s under US Department of Defense sponsorship; became IEEE Standard 1076. Strongly typed, verbose syntax influenced by Ada.
• Verilog HDL: Created by Gateway Design Automation in 1984; standardized as IEEE 1364 in 1995. C-like concise syntax; dominant in commercial semiconductor ASIC design.
• SystemVerilog: Standardized as IEEE 1800, merging Verilog with advanced object-oriented verification and assertion capabilities.

B. Typical HDL-Based Design Flow

Modern electronic design automation (EDA) follows a rigorous automated pipeline:

CODECopy Code
  +---------------------------------------------------------------+
  | Specification & Architectural Modeling                        |
  +---------------------------------------------------------------+
                                 |
                                 v
  +---------------------------------------------------------------+
  | RTL Design (Verilog / VHDL Coding)                            |
  +---------------------------------------------------------------+
                                 |
                                 v
  +---------------------------------------------------------------+
  | Behavioral Functional Simulation (ModelSim, VCS, Icarus)      |
  +---------------------------------------------------------------+
                                 |
                                 v
  +---------------------------------------------------------------+
  | Logic Synthesis (Translates RTL to Gate-Level Netlist)        |
  +---------------------------------------------------------------+
                                 |
                                 v
  +---------------------------------------------------------------+
  | Gate-Level Simulation & Static Timing Analysis (STA)          |
  +---------------------------------------------------------------+
                                 |
                                 v
  +---------------------------------------------------------------+
  | Place and Route (P&R) / Technology Mapping (FPGA / ASIC GDSII)|
  +---------------------------------------------------------------+

6. Contrasting HDLs with Software Programming Languages

7. Fundamental Verilog Constructs & Modeling Paradigms

Verilog architectures support three abstraction levels:

1. Structural / Gate-Level: Instantiating primitive logic gates (and, or, not, xor).
2. Dataflow Modeling: Continuous assignments using assign statements modeling combinational circuits:

   verilogCopy Code
   module full_adder(input a, input b, input cin, output sum, output cout);
       assign sum = a ^ b ^ cin;
       assign cout = (a & b) | (b & cin) | (a & cin);
   endmodule
   

3. Behavioral Modeling: Algorithmic descriptions encapsulated inside procedural blocks (always, initial):

   verilogCopy Code
   // D Flip-Flop with Active-High Asynchronous Reset
   module d_ff(input clk, input reset, input d, output reg q);
       always @(posedge clk or posedge reset) begin
           if (reset)
               q <= 1'b0;
           else
               q <= d;
       end
   endmodule
   

Blocking (=) vs. Non-Blocking (<=) Assignments:

• Blocking Assignment (=): Evaluated sequentially in order of appearance. Used strictly for Combinational Logic.
• Non-Blocking Assignment (<=): Evaluated in parallel at the end of the simulation time-step. Mandated for Sequential Logic (Registers, Flip-Flops) to prevent simulation race conditions.

8. Summary & Key Review Takeaways

• Register Transfer Language (RTL) models data flow between registers, control lines, and memory buffers.
• Common buses reduce routing interconnects using $N \times 1$ MUXes or Three-State Hi-Z buffers.
• Micro-operations are atomic single-clock operations: Arithmetic (add, subtract), Logic (bitwise), and Shift (logical, circular, arithmetic).
• Arithmetic shift right preserves the sign bit; arithmetic shift left monitors overflow using $V = R_{n-1} \oplus R_{n-2}$.
• Booth's algorithm multiplies signed integers in 2's complement using $Q_0, Q_{-1}$ bit-pair evaluation and arithmetic right shifts.
• HDLs model concurrent physical hardware circuits, contrasting fundamentally with sequential software execution.
• Verilog distinguishes between combinational continuous assignments (assign, =) and sequential clock-edge procedural blocks (always @(posedge clk), <=).