Unit 1: Computer Organization and the Basic Computer Architecture

1. Stored Program Organization and Instruction Codes

Modern general-purpose digital computers are based on the von Neumann architecture (stored-program concept), where instructions and data reside in a shared read-write memory unit.

1.1 Instruction Code Hierarchy

An instruction code is a group of bits that commands the central processing unit (CPU) to perform a specific elementary microoperation.

Operation Code (Opcode): A group of bits that defines the operation (e.g., ADD, SUB, AND, LDA, STA). For an instruction set with $2^n$ distinct operations, at least $n$ opcode bits are required.
Address Field: Specifies the memory location of the operand, a processor register, or an immediate constant.
Addressing Mode Bit ( $I$ ): Dictates how the address field is interpreted to determine the Effective Address (EA) of the operand.

CODE
+-------------------+----------------------+---------------------------------------+
|  Bit 15 (Mode I)  | Bits 14-12 (Opcode)  | Bits 11-0 (Address Field)             |
+-------------------+----------------------+---------------------------------------+
| 0 = Direct Addr   | 3 bits (000 to 111)  | 12 bits (Specifies memory address     |
| 1 = Indirect Addr |                      |          from 0x000 to 0xFFF = 4096)  |
+-------------------+----------------------+---------------------------------------+

1.2 Direct vs. Indirect Addressing

In Mano's Basic Computer architecture (16-bit word length, 4096-word memory):

Direct Addressing ( $I = 0$ ):
- The 12-bit address field directly contains the Effective Address (EA) of the target operand in memory.
- $\text{Effective Address (EA)} = \text{Address Field}$ .
- Requires exactly one memory access cycle during instruction execution.
Indirect Addressing ( $I = 1$ ):
- The 12-bit address field points to a memory word that holds the actual Effective Address of the operand.
- $\text{Effective Address (EA)} = M[\text{Address Field}]$ .
- Requires an extra memory read cycle during decoding to fetch the target address pointer.

CODE
DIRECT ADDRESSING (I = 0):
Instruction: [ I=0 | Opcode | 0x300 ]
Address 0x300 in Memory contains: [ OPERAND DATA = 45 ]
==> Effective Address = 0x300.

INDIRECT ADDRESSING (I = 1):
Instruction: [ I=1 | Opcode | 0x300 ]
Address 0x300 in Memory contains: [ 0x750 ]  <-- Pointer
Address 0x750 in Memory contains: [ OPERAND DATA = 99 ]
==> Effective Address = 0x750.

2. Computer Registers of the Basic Computer

To execute instructions, the CPU maintains dedicated high-speed flip-flop storage arrays called registers.

CODE
+----------+-------+-----------------------------+------------------------------------------------------+
| Register | Bits  | Full Register Name          | Primary Functional Purpose                           |
+----------+-------+-----------------------------+------------------------------------------------------+
| DR       | 16    | Data Register               | Holds memory operand read from RAM                   |
| AR       | 12    | Address Register            | Holds target address for memory read/write cycles    |
| AC       | 16    | Accumulator Register        | General-purpose computational and logic register     |
| IR       | 16    | Instruction Register        | Holds the fetched instruction code during decoding   |
| PC       | 12    | Program Counter             | Holds address of the next sequential instruction     |
| TR       | 16    | Temporary Register          | Scratches intermediate calculations without loss     |
| INPR     | 8     | Input Register              | Receives 8-bit character data from serial input      |
| OUTR     | 8     | Output Register             | Holds 8-bit character data to be printed/displayed   |
+----------+-------+-----------------------------+------------------------------------------------------+

Register Sizing Principles

12-bit Registers ( $AR, PC$ ): Memory contains $4096 = 2^{12}$ distinct locations. Therefore, any register tasked with addressing memory directly must be at least 12 bits wide.
16-bit Registers ( $DR, AC, IR, TR$ ): Memory word width is 16 bits. When memory is read, full 16-bit words are transferred into $DR$ or $IR$ .
8-bit Registers ( $INPR, OUTR$ ): Aligned with standard 8-bit alphanumeric ASCII character coding.

3. Common Bus System Architecture

In a digital computer, connecting every register output directly to every register input requires $(N \times (N-1))$ interconnect wires, leading to routing congestion and excessive hardware cost. A Common Bus System provides a shared communication path.

3.1 Multiplexer-Based Bus Design

In the 16-bit Basic Computer, the common bus consists of 16 parallel lines managed by sixteen $8 \times 1$ multiplexers (MUX).

Selection Inputs ( $S_2, S_1, S_0$ ): Three binary control lines determine which register or memory unit places its 16-bit outputs onto the shared bus.
When an addressed register is selected, its outputs are routed onto the bus lines.
Destination Loading: The target register whose LD (Load) control input is asserted ( $LD = 1$ ) latches the data off the common bus at the next positive clock edge.

CODE
+----+----+----+------------------------------------------+
| S2 | S1 | S0 | Register / Component Selected onto Bus   |
+----+----+----+------------------------------------------+
| 0  | 0  | 0  | None (Bus is floating/inactive)          |
| 0  | 0  | 1  | AR (Address Register - 12 bits zero-ext) |
| 0  | 1  | 0  | PC (Program Counter - 12 bits zero-ext)  |
| 0  | 1  | 1  | DR (Data Register - 16 bits)             |
| 1  | 0  | 0  | AC (Accumulator Register - 16 bits)      |
| 1  | 0  | 1  | IR (Instruction Register - 16 bits)      |
| 1  | 1  | 0  | TR (Temporary Register - 16 bits)        |
| 1  | 1  | 1  | Memory Unit (M[AR] - Read asserted)      |
+----+----+----+------------------------------------------+

CODE
                        THE COMMON BUS ARCHITECTURE (16 BITS)
            =============================================================
             ^        ^        ^        ^        ^        ^        ^
             |        |        |        |        |        |        |
           [ AR ]   [ PC ]   [ DR ]   [ AC ]   [ IR ]   [ TR ]  [ MEMORY ]
             |        |        |        |        |        |        |
             +--------+--------+--------+--------+--------+--------+
                                        ^
                                        | (Select S2 S1 S0)
                                [ 16x 8-to-1 MUX ]

3.2 Three-State Bus Buffers

An alternative to multiplexer-based buses is the use of three-state (tri-state) gates:

Logic 0
Logic 1
High-Impedance State (High-Z): Behaves like an open circuit (disconnected).
Tri-state buffers allow multiple register outputs to be physically tied to a common wire, provided control logic enables only one buffer at any clock pulse ( $E = 1$ ).

4. Computer Instruction Taxonomy

The Basic Computer classifies instructions into three mutually exclusive categories based on the 3-bit opcode (bits 14–12) and the mode bit (bit 15).

CODE
+------------------------------------+-----------+--------+---------------------------------------+
| Instruction Category               | Opcode    | Bit 15 | Hex Representation                    |
+------------------------------------+-----------+--------+---------------------------------------+
| Memory-Reference Instruction (MRI) | 000 - 110 | I = 0  | 0xxx through 6xxx (Direct)            |
|                                    | 000 - 110 | I = 1  | 8xxx through Exxx (Indirect)          |
+------------------------------------+-----------+--------+---------------------------------------+
| Register-Reference Instruction(RRI)| 111 (D7=1)| I = 0  | 7xxx (e.g., 7800 = CLA, 7400 = CLE)   |
+------------------------------------+-----------+--------+---------------------------------------+
| Input-Output Instruction (IOI)     | 111 (D7=1)| I = 1  | Fxxx (e.g., F800 = INP, F400 = OUT)   |
+------------------------------------+-----------+--------+---------------------------------------+

4.1 Memory-Reference Instructions (MRI)

MRIs perform operations using data stored in RAM:

AND: Bitwise logic AND with AC ( $AC \leftarrow AC \land M[AR]$ )
ADD: Binary addition with AC ( $AC \leftarrow AC + M[AR], E \leftarrow C_{out}$ )
LDA: Load word from memory into AC ( $AC \leftarrow M[AR]$ )
STA: Store Accumulator contents into memory ( $M[AR] \leftarrow AC$ )
BUN: Branch Unconditionally ( $PC \leftarrow AR$ )
BSA: Branch and Save Return Address ( $M[AR] \leftarrow PC, PC \leftarrow AR + 1$ )
ISZ: Increment Memory operand and Skip next instruction if Zero ( $M[AR] \leftarrow M[AR] + 1$ , if $M[AR] = 0$ then $PC \leftarrow PC + 1$ )

4.2 Register-Reference Instructions (RRI)

Recognized when Opcode $= 111$ ( $D_7 = 1$ ) and $I = 0$ (Hex prefix 7):

CLA (7800): Clear AC to zero ( $AC \leftarrow 0$ )
CLE (7400): Clear Extended Carry bit ( $E \leftarrow 0$ )
CMA (7200): Complement AC (1's complement) ( $AC \leftarrow \overline{AC}$ )
CME (7100): Complement E flip-flop ( $E \leftarrow \overline{E}$ )
CIR (7080): Circulate Right AC and E ( $AC \leftarrow \text{shr}(AC), AC[15] \leftarrow E, E \leftarrow AC[0]$ )
CIL (7040): Circulate Left AC and E ( $AC \leftarrow \text{shl}(AC), AC[0] \leftarrow E, E \leftarrow AC[15]$ )
INC (7020): Increment AC ( $AC \leftarrow AC + 1$ )
SPA (7010): Skip next instruction if AC is positive ( $AC[15] = 0$ )
SNA (7008): Skip next instruction if AC is negative ( $AC[15] = 1$ )
SZA (7004): Skip next instruction if AC is zero ( $AC = 0$ )
SZE (7002): Skip next instruction if E is zero ( $E = 0$ )
HLT (7001): Halt processing clock loop ( $S \leftarrow 0$ )

4.3 Input-Output Instructions (IOI)

Recognized when Opcode $= 111$ ( $D_7 = 1$ ) and $I = 1$ (Hex prefix F):

INP (F800): Input character ( $AC[7:0] \leftarrow INPR, FGI \leftarrow 0$ )
OUT (F400): Output character ( $OUTR \leftarrow AC[7:0], FGO \leftarrow 0$ )
SKI (F200): Skip if input flag is set (if $FGI = 1$ then $PC \leftarrow PC + 1$ )
SKO (F100): Skip if output flag is set (if $FGO = 1$ then $PC \leftarrow PC + 1$ )
ION (F080): Interrupt On ( $IEN \leftarrow 1$ )
IOF (F040): Interrupt Off ( $IEN \leftarrow 0$ )

5. Timing, Control Unit, and the Instruction Cycle

All internal register transfers are synchronized by master clock pulses and driven by a hardwired or microprogrammed Control Unit.

CODE
             HARDWIRED CONTROL UNIT STRUCTURE
   Instruction Register (IR)
   +---+-----+-------------+
   | I | Op  |   Address   |
   +---+-----+-------------+
     |    |
     |    v
     |  [ 3x8 Decoder ] ----> D0, D1, D2, ..., D7
     v
   [ Control Logic Gates ] <---- Master Clock Pulses
     ^
     |  [ 4x16 Decoder ] <---- Sequence Counter (SC) (4-bit: counts 0000 to 1111)

5.1 The Instruction Cycle Phases

The CPU executes a continuous sequence of instruction cycles composed of four discrete phases:

Fetch: Instruction word retrieved from RAM into $IR$ .
Decode: Opcode is decoded by $3 \times 8$ decoder; mode bit $I$ is evaluated.
Effective Address Calculation: If $I = 1$ (indirect), a memory read fetches the operand pointer.
Execution: Control signals activate arithmetic/logic gates or bus transfers.

5.2 Register Transfer Language (RTL) of Fetch & Decode

Time $T_0$ :
$T_0: AR \leftarrow PC$
(Address of next instruction placed into Address Register)
Time $T_1$ :
$T_1: IR \leftarrow M[AR], \quad PC \leftarrow PC + 1$
(Instruction word read from RAM into Instruction Register; PC incremented)
Time $T_2$ :
$T_2: D_0, \dots, D_7 \leftarrow \text{Decode}(IR[14:12]), \quad AR \leftarrow IR[11:0], \quad I \leftarrow IR[15]$
(Opcode decoded; address field transferred to AR; mode bit latched)
Time $T_3$ (Effective Address Determination):
- If Memory-Reference Indirect ( $D_7' I T_3$ ):
  $AR \leftarrow M[AR]$
- If Memory-Reference Direct ( $D_7' I' T_3$ ):
  $\text{Nothing (AR already holds Effective Address)}$
- If Register-Reference ( $D_7 I' T_3$ ):
  $\text{Execute register microoperation, } SC \leftarrow 0$
- If Input-Output ( $D_7 I T_3$ ):
  $\text{Execute I/O microoperation, } SC \leftarrow 0$

6. Input-Output Configuration and Interrupt Mechanism

6.1 Programmed I/O vs. Interrupt-Driven I/O

Programmed I/O: The CPU continually loops in a "busy-wait" polling routine, testing flag flip-flops ( $FGI, FGO$ ). Because mechanical peripherals operate millions of times slower than electronic CPU clocks, polling wastes colossal CPU compute cycles.
Interrupt Facility: When an external peripheral finishes receiving or transmitting a character, it asserts an interrupt hardware signal ( $R \leftarrow 1$ ), immediately suspending current program execution to handle the request.

CODE
+-------------------------------------------------------------------------------+
|                       INTERRUPT CYCLE STATE TRANSITION                        |
|                                                                               |
| Normal Execution Cycle (R = 0)                   Interrupt Cycle (R = 1)      |
|           |                                                 |                 |
|           v                                                 v                 |
| Check: Is IEN == 1 AND (FGI == 1 OR FGO == 1)?   T0': AR <- 0, TR <- PC       |
| If YES -> Set R = 1 (Enter Interrupt Cycle)      T1': M[AR] <- TR, PC <- 0    |
|                                                  T2': PC <- PC + 1, IEN <- 0, |
|                                                       R <- 0, SC <- 0         |
|                                                             |                 |
|                                                             v                 |
|                                                  Program branches to address 1|
|                                                  (Interrupt Service Routine)  |
+-------------------------------------------------------------------------------+

6.2 The Interrupt Cycle RTL

When an interrupt is triggered, the CPU executes the interrupt cycle instead of fetching the next sequential instruction:

$T_0'$ : $AR \leftarrow 0, \quad TR \leftarrow PC$ (Address 0 selected; return address preserved in TR)
$T_1'$ : $M[AR] \leftarrow TR, \quad PC \leftarrow 0$ (Return address stored at memory location 0; PC reset to 0)
$T_2'$ : $PC \leftarrow PC + 1, \quad IEN \leftarrow 0, \quad R \leftarrow 0, \quad SC \leftarrow 0$ (PC becomes 1; Interrupts disabled; Interrupt flag cleared; Sequence counter reset)

At address 1, the programmer places an indirect branch BUN 0 I at the end of the Interrupt Service Routine (ISR) to resume the interrupted main program.

7. The Little Man Computer (LMC) Pedagogical Model

Developed by Dr. Stuart Madnick in 1965, the Little Man Computer (LMC) models von Neumann architecture using a simplified human metaphor.

CODE
+-------------------+-----------------------------------+---------------------------------------+
| LMC Component     | Physical Hardware Equivalent      | Operational Role                      |
+-------------------+-----------------------------------+---------------------------------------+
| The Little Man    | Control Unit (CU) & ALU           | Fetches, decodes, and executes codes  |
| 100 Mailboxes     | Random Access Memory (RAM)        | Holds 3-digit decimal words (00 - 99) |
| Calculator        | Accumulator (AC)                  | Displays and accumulates arithmetic   |
| Instruction Counter| Program Counter (PC)             | Keeps track of next mailbox number    |
| In-Basket         | Input Register (INPR)             | Receives numbers typed by user        |
| Out-Basket        | Output Register (OUTR)            | Delivers processed results to user    |
+-------------------+-----------------------------------+---------------------------------------+

7.1 LMC 3-Digit Instruction Format

Each instruction in the LMC is a 3-digit decimal number:

First Digit: Operation Code ( $0$ to $9$ ).
Last Two Digits: Mailbox Address ( $00$ to $99$ ).

CODE
+----------+-------+----------------------------------------------------------------------------+
| Mnemonic | Code  | Operational Description                                                    |
+----------+-------+----------------------------------------------------------------------------+
| HLT / COB| 000   | Halt / Coffee Break (Stops execution)                                      |
| ADD      | 1xx   | Add content of mailbox xx to Calculator                                    |
| SUB      | 2xx   | Subtract content of mailbox xx from Calculator                             |
| STA      | 3xx   | Store content of Calculator into mailbox xx                                |
| LDA      | 5xx   | Load content of mailbox xx into Calculator                                 |
| BRA      | 6xx   | Branch Always (Unconditional Jump to mailbox xx)                           |
| BRZ      | 7xx   | Branch if Zero (Jump to mailbox xx if Calculator is 000)                   |
| BRP      | 8xx   | Branch if Positive (Jump to mailbox xx if Calculator >= 0)                 |
| INP      | 901   | Input: Move value from In-Basket into Calculator                           |
| OUT      | 902   | Output: Copy value from Calculator to Out-Basket                           |
| DAT      | ---   | Data declaration (Reserves mailbox without executable opcode)               |
+----------+-------+----------------------------------------------------------------------------+

Computer Organization And Design